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PIC12F635/PIC16F636/639 Data Sheet
8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology
*8-bit, 8-pin Devices Protected by Microchip's Low Pin Count Patent: U. S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.
(c) 2007 Microchip Technology Inc. DS41232D
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41232D-page ii
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers With nanoWatt Technology
High-Performance RISC CPU:
* Only 35 instructions to learn: - All single-cycle instructions except branches * Operating speed: - DC - 20 MHz oscillator/clock input - DC - 200 ns instruction cycle * Interrupt capability * 8-level deep hardware stack * Direct, Indirect and Relative Addressing modes
Peripheral Features:
* 6/12 I/O pins with individual direction control: - High-current source/sink for direct LED drive - Interrupt-on-change pin - Individually programmable weak pull-ups/ pull-downs - Ultra Low-Power Wake-up * Analog Comparator module with: - Up to two analog comparators - Programmable On-chip Voltage Reference (CVREF) module (% of VDD) - Comparator inputs and outputs externally accessible * Timer0: 8-bit timer/counter with 8-bit programmable prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Timer1 Gate (count enable) - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected * KEELOQ(R) compatible hardware Cryptographic module * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins
Special Microcontroller Features:
* Precision Internal Oscillator: - Factory calibrated to 1%, typical - Software selectable frequency range of 8 MHz to 125 kHz - Software tunable - Two-Speed Start-up mode - Crystal fail detect for critical applications - Clock mode switching during operation for power savings * Clock mode switching for low-power operation * Power-Saving Sleep mode * Wide operating voltage range (2.0V-5.5V) * Industrial and Extended Temperature range * Power-on Reset (POR) * Wake-up Reset (WUR) * Independent weak pull-up/pull-down resistors * Programmable Low-Voltage Detect (PLVD) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Reset (BOR) with software control option * Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable * Multiplexed Master Clear with pull-up/input pin * Programmable code protection (program and data independent) * High-Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM Retention: > 40 years
Low-Frequency Analog Front-End Features (PIC16F639 only):
* Three input pins for 125 kHz LF input signals * High input detection sensitivity (3 mVPP, typical) * Demodulated data, Carrier clock or RSSI output selection * Input carrier frequency: 125 kHz, typical * Input modulation frequency: 4 kHz, maximum * 8 internal Configuration registers * Bidirectional transponder communication (LF talk back) * Programmable antenna tuning capacitance (up to 63 pF, 1 pF/step) * Low standby current: 5 A (with 3 channels enabled), typical * Low operating current: 15 A (with 3 channels enabled), typical * Serial Peripheral Interface (SPI) with internal MCU and external devices * Supports Battery Back-up mode and batteryless operation with external circuits
Low-Power Features:
* Standby Current: - 1 nA @ 2.0V, typical * Operating Current: - 8.5 A @ 32 kHz, 2.0V, typical - 100 A @ 1 MHz, 2.0V, typical * Watchdog Timer Current: - 1 A @ 2.0V, typical
(c) 2007 Microchip Technology Inc.
DS41232D-page 1
PIC12F635/PIC16F636/639
Program Memory Device Flash (words) PIC12F635 PIC16F636 PIC16F639 1024 2048 2048 SRAM (bytes) 64 128 128 EEPROM (bytes) 128 256 256 6 12 12 1 2 2 Data Memory I/O Comparators Low Frequency Analog Front-End N N Y
Note 1: Any references to PORTA, RAn, TRISA and TRISAn refer to GPIO, GPn, TRISIO and TRISIOn, respectively. 2: VDDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in this document unless otherwise stated. 3: VSST is the ground reference voltage of the Analog Front-End section (PIC16F639 only). VSST is treated as VSS in this document unless otherwise stated.
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(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
8-Pin Diagrams (PDIP, SOIC, DFN, DFN-S)
PDIP, SOIC VDD GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/VPP 1 PIC12F635 2 3 4 8 7 6 5 VSS GP0/C1IN+/ICSPDAT/ULPWU GP1/C1IN-/ICSPCLK GP2/T0CKI/INT/C1OUT
DFN, DFN-S VDD GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/VDD 1 2 3 4 8 7 6 5 VSS GP0/CIN+/ICSPDAT/ULPWU GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT
TABLE 1:
I/O GP0 GP1 GP2 GP3(1) GP4 GP5 -- -- Note 1: 2: Pin 7 6 5 4 3 2 1 8
8-PIN SUMMARY (PDIP, SOIC, DFN, DFN-S)
Comparators C1IN+ C1INC1OUT -- -- -- -- -- Timer -- -- T0CKI -- T1G T1CKI -- -- Interrupts IOC IOC INT/IOC IOC IOC IOC -- -- Pull-ups Y Y Y Y(2) Y Y -- -- Basic ICSPDAT/ULPWU ICSPCLK -- MCLR/VPP OSC2/CLKOUT OSC1/CLKIN VDD VSS
Input only. Only when pin is configured for external MCLR.
(c) 2007 Microchip Technology Inc.
PIC12F635
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PIC12F635/PIC16F636/639
14-Pin Diagram (PDIP, SOIC, TSSOP)
VDD RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5 RC4/C2OUT RC3
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/T0CKI/INT/C1OUT RC0/C2IN+ RC1/C2INRC2
TABLE 2:
I/O RA0 RA1 RA2 RA3 RA4 RA5 RC0 RC1 RC2 RC3 RC4 RC5 -- -- Note 1: 2:
(1)
14-PIN SUMMARY (PDIP, SOIC, TSSOP)
Pin 13 12 11 4 3 2 10 9 8 7 6 5 1 14 Comparators C1IN+ C1INC1OUT -- -- -- C2IN+ C2IN-- -- C2OUT -- -- -- Timer -- -- T0CKI -- T1G T1CKI -- -- -- -- -- -- -- -- Interrupts IOC IOC INT/IOC IOC IOC IOC -- -- -- -- -- -- -- -- Pull-ups Y Y Y Y(2) Y Y -- -- -- -- -- -- -- -- Basic ICSPDAT/ULPWU VREF/ICSPCLK -- MCLR/VPP OSC2/CLKOUT OSC1/CLKIN -- -- -- -- -- -- VDD VSS
Input only. Only when pin is configured for external MCLR.
PIC16F636
DS41232D-page 4
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
16-Pin Diagram
QFN VDD VSS 13 12 NC 15 NC 14
16
RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5
1
RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/T0CKI/INT/C1OUT RC0/C2IN+
2 PIC16F636 11 10 3 4 5 6 7 RC2 8 RC1/C2IN9
RC4/C2OUT
TABLE 3:
I/O RA0 RA1 RA2 RA3(1) RA4 RA5 RC0 RC1 RC2 RC3 RC4 RC5 -- -- -- -- Note 1: 2: Pin 12 11 10 3 2 1 9 8 7 6 5 4 16 13 14 15
16-PIN SUMMARY
Comparators C1IN+ C1INC1OUT -- -- -- C2IN+ C2IN-- -- C2OUT -- -- -- -- -- Timer -- -- T0CKI -- T1G T1CKI -- -- -- -- -- -- -- -- -- -- Interrupts IOC IOC INT/IOC IOC IOC IOC -- -- -- -- -- -- -- -- -- -- Pull-ups Y Y Y Y(2) Y Y -- -- -- -- -- -- -- -- -- -- Basic ICSPDAT/ULPWU VREF/ICSPCLK -- MCLR/VPP OSC2/CLKOUT OSC1/CLKIN -- -- -- -- -- -- VDD VSS NC NC
Input only. Only when pin is configured for external MCLR.
(c) 2007 Microchip Technology Inc.
RC3
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PIC12F635/PIC16F636/639
20-Pin Diagram
SSOP
VDD RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5 RC4/C2OUT RC3/LFDATA/RSSI/CCLK/SDIO VDDT(3) LCZ LCY
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/TOCKI/INT/C1OUT RC0/C2IN+ RC1/C2IN-/CS RC2/SCLK/ALERT VSST(4) LCCOM LCX
TABLE 4:
I/O RA0 RA1 RA2 RA3(1) RA4 RA5 RC0 RC1 RC2 RC3 RC4 RC5 -- -- -- -- -- -- -- -- Note 1: 2: 3: 4: Pin 19 18 17 4 3 2 16 15 14 7 6 5 8 13 11 10 9 12 1 20
20-PIN SUMMARY
Analog Front-End -- -- -- -- -- -- -- -- ALERT LFDATA/RSSI -- -- -- -- LCX LCY LCZ LCCOM -- -- Comparators C1IN+ C1INC1OUT -- -- -- C2IN+ C2IN-- -- C2OUT -- -- -- -- -- -- -- -- -- Timer -- -- T0CKI -- T1G T1CKI -- -- -- -- -- -- -- -- -- -- -- -- -- -- Interrupts IOC IOC INT/IOC IOC IOC IOC -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pull-ups Y Y Y Y(2) Y Y -- -- -- -- -- -- -- -- -- -- -- -- -- -- Basic ICSPDAT/ULPWU VREF/ICSPCLK -- MCLR/VPP OSC2/CLKOUT OSC1/CLKIN -- CS SCLK CCLK/SDIO -- -- VDDT(3) VSST(4) -- -- -- -- VDD VSS
Input only. Only when pin is configured for external MCLR. VDDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in this document unless otherwise stated. VSST is the ground reference voltage of the Analog Front-End section (PIC16F639 only). VSST is treated as VSS in this document unless otherwise stated.
PIC16F639
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(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Memory Organization ................................................................................................................................................................. 17 3.0 Clock Sources ............................................................................................................................................................................ 35 4.0 I/O Ports ..................................................................................................................................................................................... 47 5.0 Timer0 Module ........................................................................................................................................................................... 61 6.0 Timer1 Module with Gate Control............................................................................................................................................... 64 7.0 Comparator Module.................................................................................................................................................................... 71 8.0 Programmable Low-Voltage Detect (PLVD) Module.................................................................................................................. 87 9.0 Data EEPROM Memory ............................................................................................................................................................. 91 10.0 KEELOQ(R) Compatible Cryptographic Module ............................................................................................................................. 95 11.0 Analog Front-End (AFE) Functional Description (PIC16F639 Only) .......................................................................................... 97 12.0 Special Features of the CPU.................................................................................................................................................... 129 13.0 Instruction Set Summary .......................................................................................................................................................... 149 14.0 Development Support............................................................................................................................................................... 159 15.0 Electrical Specifications............................................................................................................................................................ 163 16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 191 17.0 Packaging Information.............................................................................................................................................................. 211 On-Line Support 223 Systems Information and Upgrade Hot Line ..................................................................................................................................... 223 Reader Response ............................................................................................................................................................................. 224 Appendix A: Data Sheet Revision History......................................................................................................................................... 225 Product Identification System ........................................................................................................................................................... 231 Worldwide Sales and Service ........................................................................................................................................................... 232
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(c) 2007 Microchip Technology Inc.
DS41232D-page 7
PIC12F635/PIC16F636/639
NOTES:
DS41232D-page 8
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
1.0 DEVICE OVERVIEW
Block Diagrams and pinout descriptions of the devices are as follows: * PIC12F635 (Figure 1-1, Table 1-1) * PIC16F636 (Figure 1-2, Table 1-2) * PIC16F639 (Figure 1-3, Table 1-3) This document contains device specific information for the PIC12F635/PIC16F636/639 devices.
FIGURE 1-1:
PIC12F635 BLOCK DIAGRAM
Configuration 13 Program Counter Flash 1K x 14 Program Memory Data Bus 8 GPIO
GP0 GP1 GP2 GP3 GP4 GP5
8-level Stack (13-bit)
RAM 64 bytes File Registers RAM Addr 9
Program Bus
14
Instruction Reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR Reg STATUS Reg
8 3
Instruction Decode and Control OSC1/CLKIN Timing Generation OSC2/CLKOUT 8 MHz Internal Oscillator 31 kHz Internal Oscillator
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Programmable Low-Voltage Detect Wake-up Reset
MUX
ALU 8 W Reg
T1G MCLR VDD T1CKI Timer0 T0CKI Timer1 VSS
Cryptographic Module
1 Analog Comparator and Reference
EEDAT 128 bytes Data EEPROM EEADDR
C1IN- C1IN+ C1OUT
(c) 2007 Microchip Technology Inc.
DS41232D-page 9
PIC12F635/PIC16F636/639
FIGURE 1-2: PIC16F636 BLOCK DIAGRAM
Configuration 13 Program Counter Flash 2K x 14 Program Memory Data Bus 8 PORTA
RA0 RA1
8-level Stack (13-bit)
Program Bus
RAM 128 bytes File Registers RAM Addr 9
RA2 RA3 RA4 RA5
14 Instruction Reg Direct Addr 7
Addr MUX 8 Indirect Addr PORTC
RC0 RC1 RC2 RC3 RC4 RC5
FSR Reg STATUS Reg 8 3
Instruction Decode and Control OSC1/CLKIN Timing Generation OSC2/CLKOUT 8 MHz Internal Oscillator 31 kHz Internal Oscillator
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Programmable Low-Voltage Detect Wake-up Reset
MUX
ALU 8 W Reg
T1CKI
T1G
MCLR Timer0 T0CKI
VDD
VSS Timer1
Cryptographic Module
2 Analog Comparators and Reference
EEDAT 256 bytes Data EEPROM EEADDR
C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
DS41232D-page 10
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 1-3: PIC16F639 BLOCK DIAGRAM
Configuration 13 Program Counter Flash 2K x 14 Program Memory Data Bus 8 PORTA RA0 RA1 8-level Stack (13-bit) RAM 128 bytes File Registers RAM Addr (1) 9 PORTC Direct Addr 7 8 Indirect Addr RC0 RC1 RC2 RC3 RC4 RC5 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Programmable Low-voltage Detect Wake-up Reset 3 MUX RA2 RA3 RA4 RA5
Program Bus
14 Instruction Reg
Addr MUX
FSR Reg STATUS Reg 8
Instruction Decode and Control OSC1/CLKIN Timing Generation OSC2/CLKOUT 8 MHz Internal Oscillator 31 kHz Internal Oscillator
ALU 8 W Reg VDDT VSST LCCOM T1CKI T1G 125 kHz Analog Front-End (AFE)
LCX MCLR VDD Timer0 T0CKI VSS Timer1
LCY
LCZ
KEELOQ Module
2 Analog Comparators and Reference
EEDAT 256 bytes DATA EEPROM EEADDR
C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
(c) 2007 Microchip Technology Inc.
DS41232D-page 11
PIC12F635/PIC16F636/639
TABLE 1-1: PIC12F635 PINOUT DESCRIPTIONS
Function GP0 Input Type TTL Output Type -- Description General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin. Comparator 1 input - positive. Serial programming data I/O. Ultra Low-Power Wake-up input. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Comparator 1 input - negative. Serial programming clock. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. External clock for Timer0. External interrupt. Comparator 1 output. General purpose input. Individually controlled interrupt-on-change. Master Clear Reset. Pull-up enabled when configured as MCLR. Programming voltage. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Timer1 gate. XTAL connection. TOSC/4 reference clock. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Timer1 clock. XTAL connection. TOSC reference clock. Power supply for microcontroller. Ground reference for microcontroller. D = Direct Name GP0/C1IN+/ICSPDAT/ULPWU
C1IN+ ICSPDAT ULPWU GP1/C1IN-/ICSPCLK GP1 C1INICSPCLK GP2/T0CKI/INT/C1OUT GP2 T0CKI INT C1OUT GP3/MCLR/VPP GP3 MCLR VPP GP4/T1G/OSC2/CLKOUT GP4 T1G OSC2 CLKOUT GP5/T1CKI/OSC1/CLKIN GP5 T1CKI OSC1 CLKIN VDD VSS Legend: VDD VSS AN = Analog input or output HV = High Voltage TTL = TTL compatible input
AN TTL AN TTL AN ST ST ST ST -- TTL ST HV TTL ST -- -- TTL ST XTAL ST D D
-- CMOS -- CMOS -- -- CMOS -- -- CMOS -- -- -- CMOS -- XTAL CMOS CMOS -- -- -- -- --
CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal
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(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 1-2:
Name RA0/C1IN+/ICSPDAT/ULPWU
PIC16F636 PINOUT DESCRIPTIONS
Function RA0 Input Type TTL Output Type -- Description General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin. Comparator 1 input - positive. Serial programming data I/O. Ultra Low-Power Wake-up input. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Comparator 1 input - negative. External voltage reference Serial programming clock. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. External clock for Timer0. External interrupt. Comparator 1 output. General purpose input. Individually controlled interrupt-on-change. Master Clear Reset. Pull-up enabled when configured as MCLR. Programming voltage. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Timer1 gate. XTAL connection. TOSC/4 reference clock. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Timer1 clock. XTAL connection. TOSC reference clock. General purpose I/O. Comparator 1 input - positive. General purpose I/O. Comparator 1 input - negative. General purpose I/O. General purpose I/O. General purpose I/O. Comparator 2 output. General purpose I/O. Power supply for microcontroller. Ground reference for microcontroller. D = Direct
C1IN+ ICSPDAT ULPWU RA1/C1IN-/VREF/ICSPCLK RA1 C1INVREF ICSPCLK RA2/T0CKI/INT/C1OUT RA2 T0CKI INT C1OUT RA3/MCLR/VPP RA3 MCLR VPP RA4/T1G/OSC2/CLKOUT RA4 T1G OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN RA5 T1CKI OSC1 CLKIN RC0/C2IN+ RC1/C2INRC2 RC3 RC4/C2OUT RC5 VDD VSS Legend: RC0 C2IN+ RC1 C2INRC2 RC3 RC4 C2OUT RC5 VDD VSS AN = Analog input or output HV = High Voltage TTL = TTL compatible input
AN TTL AN TTL AN AN ST ST ST ST -- TTL ST HV TTL ST -- -- TTL ST XTAL ST TTL AN TTL AN TTL TTL TTL -- TTL D D
-- CMOS -- CMOS -- -- -- CMOS -- -- CMOS -- -- -- CMOS -- XTAL CMOS CMOS -- -- -- CMOS -- CMOS -- CMOS CMOS CMOS CMOS CMOS -- --
CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal
(c) 2007 Microchip Technology Inc.
DS41232D-page 13
PIC12F635/PIC16F636/639
TABLE 1-3:
Name LCCOM LCX LCY LCZ RA0/C1IN+/ICSPDAT/ULPWU
PIC16F639 PINOUT DESCRIPTIONS
Function LCCOM LCX LCY LCZ RA0 Input Type AN AN AN AN TTL Output Type -- -- -- -- -- Description Common reference for analog inputs. 125 kHz analog X channel input. 125 kHz analog Y channel input. 125 kHz analog Z channel input. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin. Comparator1 input - positive. Serial Programming Data IO. Ultra Low-Power Wake-up input. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Comparator1 input - negative. External voltage reference Serial Programming Clock. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. External clock for Timer0. External Interrupt. Comparator1 output. General purpose input. Individually controlled interrupt-on-change. Master Clear Reset. Pull-up enabled when configured as MCLR. Programming voltage. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Timer1 gate. XTAL connection. TOSC reference clock. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Timer1 clock. XTAL connection. TOSC/4 reference clock. General purpose I/O. Comparator1 input - positive. General purpose I/O. Comparator1 input - negative. Chip select input for SPI communication with internal pull-up resistor. General purpose I/O. Digital clock input for SPI communication. Output with internal pull-up resistor for AFE error signal. D = Direct OD = Open Drain
C1IN+ ICSPDAT ULPWU RA1/C1IN-/VREF/ICSPCLK RA1 C1INVREF ICSPCLK RA2/T0CKI/INT/C1OUT RA2 T0CKI INT C1OUT RA3/MCLR/VPP RA3 MCLR VPP RA4/T1G/OSC2/CLKOUT RA4 T1G OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN RA5 T1CKI OSC1 CLKIN RC0/C2IN+ RC0 C2IN+ RC1/C2IN-/CS RC1 C2INCS RC2/SCLK/ALERT RC2 SCLK ALERT Legend: AN = Analog input or output HV = High Voltage TTL = TTL compatible input
AN TTL AN TTL AN AN ST ST ST ST -- TTL ST HV TTL ST -- -- TTL ST XTAL ST TTL AN TTL AN TTL TTL TTL --
-- CMOS -- CMOS -- -- -- CMOS -- -- CMOS -- -- -- CMOS -- XTAL CMOS CMOS -- -- -- CMOS -- CMOS -- -- CMOS -- OD
CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal
DS41232D-page 14
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 1-3:
Name RC3/LFDATA/RSSI/CCLK/SDO
PIC16F639 PINOUT DESCRIPTIONS (CONTINUED)
Function RC3 LFDATA RSSI CCLK SDIO Input Type TTL -- -- -- TTL TTL -- TTL D D D D Output Type CMOS CMOS General purpose I/O. Digital output representation of analog input signal to LC pins. Description
Current Received signal strength indicator. Analog current that is proportional to input amplitude. -- CMOS CMOS CMOS CMOS -- -- -- -- Carrier clock output. Input/Output for SPI communication. General purpose I/O. Comparator2 output. General purpose I/O. Power supply for Analog Front-End. In this document, VDDT is treated the same as VDD, unless otherwise stated. Ground reference for Analog Front-End. In this document, VSST is treated the same as VSS, unless otherwise stated. Power supply for microcontroller. Ground reference for microcontroller. D = Direct OD = Open Drain
RC4/C2OUT RC5 VDDT VSST VDD VSS Legend:
RC4 C2OUT RC5 VDDT VSST VDD VSS
AN = Analog input or output HV = High Voltage TTL = TTL compatible input
CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal
(c) 2007 Microchip Technology Inc.
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NOTES:
DS41232D-page 16
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2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 2-1: PROGRAM MEMORY MAP AND STACK OF THE PIC12F635
PC<12:0> CALL, RETURN RETFIE, RETLW Stack Level 1 13
The PIC12F635/PIC16F636/639 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh, for the PIC12F635) and 2K x 14 (0000h-07FFh, for the PIC16F636/639) is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 2K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
Stack Level 8 Reset Vector 0000h
2.2
Data Memory Organization
Interrupt Vector
0004h 0005h
The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are GPRs, implemented as static RAM for the PIC16F636/639. For the PIC12F635, register locations 40h through 7Fh are GPRs implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns `0' when read. RP0 of the STATUS register is the bank select bit. RP1 0 0 1 1 RP0 0 1 0 1 Bank 0 is selected Bank 1 is selected Bank 2 is selected Bank 3 is selected
On-chip Program Memory 03FFh 0400h Access 0-3FFh 1FFFh
FIGURE 2-2: PROGRAM MEMORY MAP AND STACK OF THE PIC16F636/639
PC<12:0> CALL, RETURN RETFIE, RETLW Stack Level 1 13
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h 0005h
On-chip Program Memory
07FFh 0800h Access 0-7FFh 1FFFh
(c) 2007 Microchip Technology Inc.
DS41232D-page 17
PIC12F635/PIC16F636/639
2.2.1 GENERAL PURPOSE REGISTER
The register file is organized as 64 x 8 for the PIC12F635 and 128 x 8 for the PIC16F636/639. Each register is accessed, either directly or indirectly, through the File Select Register, FSR (see Section 2.4 "Indirect Addressing, INDF and FSR Registers").
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Figure 2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
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PIC12F635/PIC16F636/639
FIGURE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS
File Address Indirect addr.(1) 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISIO 85h 86h 87h 88h 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch 8Dh PCON 8Eh OSCCON 8Fh OSCTUNE 90h 91h 92h 93h LVDCON 94h WPUDA 95h IOCA 96h WDA 97h 98h VRCON 99h EEDAT 9Ah EEADR 9Bh EECON1 9Ch EECON2(1) 9Dh 9Eh 9Fh A0h File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h File Address Indirect addr.(1) 00h TMR0 01h PCL 02h STATUS 03h FSR 04h GPIO 05h 06h 07h 08h 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h 11h 12h 13h 14h 15h 16h 17h WDTCON 18h CMCON0 19h CMCON1 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h
Accesses 00h-0Bh
Accesses 80h-8Bh
CRCON CRDAT0(2) CRDAT1(2) CRDAT2(2) CRDAT3(2)
General Purpose Register 64 Bytes Bank 0
3Fh 40h EFh F0h FFh 16Fh 170h 17Fh 1EFh 1F0h 1FFh
7Fh
Accesses 70h-7Fh Bank 1
Accesses 70h-7Fh Bank 2
Accesses Bank 0 Bank 3
Unimplemented data memory locations, read as `0'. Note 1: Not a physical register. 2: CRDAT<3:0> registers are KEELOQ(R) hardware peripheral related registers and require the execution of the "KEELOQ(R) Encoder License Agreement" regarding implementation of the module and access to related registers. The "KEELOQ(R) Encoder License Agreement" may be accessed through the Microchip web site located at www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.
(c) 2007 Microchip Technology Inc.
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FIGURE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. (1) 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h 86h TRISC 87h 88h 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch 8Dh PCON 8Eh OSCCON 8Fh OSCTUNE 90h 91h 92h 93h LVDCON 94h WPUDA 95h IOCA 96h WDA 97h 98h VRCON 99h EEDAT 9Ah EEADR 9Bh EECON1 9Ch EECON2(1) 9Dh 9Eh 9Fh General A0h Purpose Register 32 Bytes BFh C0h EFh Accesses F0h 70h-7Fh FFh Bank 1 File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h File Address Indirect addr.(1) 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h 06h PORTC 07h 08h 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h 11h 12h 13h 14h 15h 16h 17h WDTCON 18h CMCON0 19h CMCON1 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh General 20h Purpose Register 96 Bytes
Accesses 00h-0Bh
Accesses 80h-8Bh
CRCON CRDAT0(2) CRDAT1(2) CRDAT2(2) CRDAT3(2)
7Fh Bank 0
Accesses 70h-7Fh Bank 2
16Fh 170h 17Fh
Accesses Bank 0 Bank 3
1EFh 1F0h 1FFh
Unimplemented data memory locations, read as `0'. Note 1: Not a physical register. 2: CRDAT<3:0> registers are KEELOQ hardware peripheral related registers and require the execution of the "KEELOQ(R) Encoder License Agreement" regarding implementation of the module and access to related registers. The "KEELOQ(R) Encoder License Agreement" may be accessed through the Microchip web site located at www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.
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PIC12F635/PIC16F636/639
TABLE 2-1:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: INDF TMR0 PCL STATUS FSR GPIO -- -- -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON -- -- -- -- -- -- -- WDTCON CMCON0 CMCON1 -- -- -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx GP4 GP3 GP2 GP1 GP0 --xx xx00 -- -- -- -- -- T0IE CRIF Write Buffer for upper 5 bits of Program Counter INTE -- RAIE C1IF T0IF OSFIF INTF -- RAIF(2) TMR1IF ---0 0000 0000 000x 000- 00-0 -- xxxx xxxx xxxx xxxx TMR1CS TMR1ON 0000 0000 -- -- -- -- -- -- -- -- -- -- WDTPS3 CINV -- WDTPS2 CIS -- WDTPS1 CM2 -- WDTPS0 CM1 T1GSS SWDTEN CM0 CMSYNC ---0 1000 -0-0 0000 ---- --10 -- -- -- -- -- 32,137 61,137 32,137 26,137 32,137 47,137 -- -- -- -- 32,137 28,137 30,137 -- 64,137 64,137 68,137 -- -- -- -- -- -- -- 144,137 79,137 82,137 -- -- -- -- -- Name
PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR/ WUR Page
Indirect Data Memory Address Pointer -- -- GP5
Unimplemented Unimplemented Unimplemented Unimplemented -- GIE EEIF -- PEIE LVDIF
Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Holding Register for the Most Significant Byte of the 16-bit TMR1 T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- COUT --
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatch exists.
(c) 2007 Microchip Technology Inc.
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TABLE 2-2:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 9Bh 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: 2: 3: INDF OPTION_REG PCL STATUS FSR TRISIO -- -- -- -- PCLATH INTCON PIE1 -- PCON OSCCON OSCTUNE -- -- -- LVDCON WPUDA(2) IOCA WDA
(2)
PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR/ WUR Page
Name
Addressing this location uses contents of FSR to address data memory (not a physical register) RAPU IRP -- INTEDG RP1 -- T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC TRISIO1 PS0 C Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer TRISIO5 TRISIO4 TRISIO3 TRISIO2 Unimplemented Unimplemented Unimplemented Unimplemented -- GIE EEIE -- -- -- -- PEIE LVDIE -- IRCF2 -- -- T0IE CRIE Write Buffer for upper 5 bits of Program Counter INTE -- RAIE C1IE WUR OSTS TUN3 T0IF OSFIE -- HTS TUN2 INTF -- POR LTS TUN1
xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx -- -- -- -- ---0 0000 RAIF(3) 0000 000x TMR1IE 000- 00-0 -- BOR SCS TUN0
32,137 63,137 32,137 26,137 32,137
TRISIO0 --11 1111 --11 1111 -- -- -- --
32,137 28,137 29,137
Unimplemented ULPWUE SBOREN IRCF1 -- IRCF0 TUN4
--
31,137 36,137 40,137
--01 q-qq -110 q000 ---0 0000 -- -- --
Unimplemented Unimplemented Unimplemented -- -- -- -- VREN -- -- -- -- -- IRVST IOCA5 WDA5 VRR LVDEN IOCA4 WDA4 -- -- -- IOCA3 -- VR3 LVDL2 IOCA2 WDA2 VR2 LVDL1 IOCA1 WDA1 VR1 LVDL0 IOCA0 WDA0 VR0 WPUDA5 WPUDA4
-- -- --
--00 -000 --00 -000
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111 --00 0000 --00 0000 --11 -111 --11 -111 -- --
-- VRCON EEDAT EEADR EECON1 EECON2 -- --
Unimplemented
0-0- 0000 0-0- 0000
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 -- -- -- -- WRERR WREN WR RD ---- x000 ---- q000 ---- ---- ---- ----- -- -- -- EEPROM Control Register 2 (not a physical register) Unimplemented Unimplemented
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. GP3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register. MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset, but will set again if the mismatch exists.
DS41232D-page 22
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PIC12F635/PIC16F636/639
TABLE 2-3:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: INDF TMR0 PCL STATUS FSR PORTA -- PORTC -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON -- -- -- -- -- -- -- WDTCON CMCON1 -- -- -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte IRP -- -- RP1 -- -- RP0 RA5 RC5 TO RA4 RC4 PD RA3 RC3 Z RA2 RC2 DC RA1 RC1 C RA0 RC0 Indirect Data Memory Address Pointer Unimplemented Unimplemented Unimplemented -- GIE EEIF -- PEIE LVDIF -- T0IE CRIF Write Buffer for upper 5 bits of Program Counter INTE C2IF RAIE C1IF T0IF OSFIF INTF -- RAIF(2) xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx xx00 -- --xx xx00 -- -- ---0 0000 0000 000x -- xxxx xxxx xxxx xxxx TMR1CS TMR1ON 0000 0000 -- -- -- -- -- -- -- -- C2INV -- WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 C1INV -- CIS -- CM2 -- CM1 T1GSS CM0 0000 0000 -- -- -- -- -- C2SYNC ---- --10
32,137 61,137 32,137 26,137 32,137 48,137
PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR/ WUR Page
Name
--
57,137
-- --
32,137 28,137 30,137
TMR1IF 0000 00-0
Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Holding Register for the Most Significant Byte of the 16-bit TMR1 T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- C1OUT --
--
64,137 64,137 68,137
-- -- -- -- -- -- --
144,137 79,137 82,137
CMCON0 C2OUT
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
-- -- -- -- --
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatch exists.
(c) 2007 Microchip Technology Inc.
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TABLE 2-4:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h INDF OPTION_REG PCL STATUS FSR TRISA -- TRISC -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RAPU IRP -- -- INTEDG RP1 -- -- T0CS RP0 TRISA5 TRISC5 T0SE TO TRISA4 TRISC4 PSA PD TRISA3 TRISC3 PS2 Z TRISA2 TRISC2 PS1 DC TRISA1 TRISC1 PS0 C Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented Unimplemented Unimplemented -- GIE EEIE -- OSCCON OSCTUNE -- -- -- LVDCON WPUDA(2) IOCA WDA
(2)
PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR/ WUR Page
Name
xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx -- -- --
32,137 63,137 32,137 26,137 32,137
TRISA0 --11 1111 --11 1111 -- -- --
32,137 28,137 29,137
TRISC0 --11 1111 --11 1111
8Ah PCLATH 8Bh INTCON 8Ch PIE1 8Dh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 9Bh 99h 8Eh PCON
-- PEIE LVDIE -- IRCF2 --
-- T0IE CRIE
Write Buffer for upper 5 bits of Program Counter INTE C2IE RAIE C1IE WUR OSTS TUN3 T0IF OSFIE -- HTS TUN2 INTF -- POR LTS TUN1 RAIF(3)
---0 0000 0000 000x --
TMR1IE 0000 00-0 BOR SCS TUN0
Unimplemented -- -- -- ULPWUE SBOREN IRCF1 -- IRCF0 TUN4
--
--01 q-qq --0u u-uu -110 q000 -110 x000 ---0 0000 ---u uuuu -- -- -- -- -- --
Unimplemented Unimplemented Unimplemented -- -- -- -- VREN -- -- -- -- -- IRVST IOCA5 WDA5 VRR LVDEN IOCA4 WDA4 -- -- -- IOCA3 -- VR3 LVDL2 IOCA2 WDA2 VR2 LVDL1 IOCA1 WDA1 VR1 EEDAT1 WR LVDL0 IOCA0 WDA0 VR0 WPUDA5 WPUDA4
--00 -000 --00 -000
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111 --00 0000 --00 0000 --11 -111 --11 -111 -- --
-- VRCON
Unimplemented EEDAT7 EEDAT6 EEDAT5 -- -- -- EEDAT4 EEDAT3 EEDAT2 -- WRERR WREN
0-0- 0000 0-0- 0000
9Ah EEDAT 9Bh EEADR 9Ch EECON1 9Dh EECON2 9Eh 9Fh Legend: Note 1: 2: 3: -- --
EEDAT0 0000 0000 0000 0000 RD ---- x000 ---- q000 ---- ---- ---- ----- -- -- --
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 EEPROM Control Register 2 (not a physical register) Unimplemented Unimplemented
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register. MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mismatch exists.
DS41232D-page 24
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 2-5:
Addr Bank 2 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h Legend: Note 1: 2: -- -- -- -- CRCON Unimplemented Unimplemented Unimplemented Unimplemented GO/DONE ENC/DEC -- -- -- -- CRREG1 -- -- -- -- -- -- -- -- Name
PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR/ WUR Page
CRREG0 00-- --00 00-- --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- --
CRDAT0(2) Cryptographic Data Register 0 CRDAT1(2) Cryptographic Data Register 1 CRDAT2 -- --
(2)
Cryptographic Data Register 2 Unimplemented Unimplemented
CRDAT3(2) Cryptographic Data Register 3
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. CRDAT<3:0> registers are KEELOQ(R) hardware peripheral related registers and require the execution of the "KEELOQ Encoder License Agreement" regarding implementation of the module and access to related registers. The "KEELOQ Encoder License Agreement" may be accessed through the Microchip web site located at www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.
(c) 2007 Microchip Technology Inc.
DS41232D-page 25
PIC12F635/PIC16F636/639
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains: * the arithmetic status of the ALU * the Reset status * the bank select bits for data memory (GPR and SFR) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see Section 13.0 "Instruction Set Summary" Note 1: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction.
REGISTER 2-1:
R/W-0 IRP bit 7 Legend: R = Readable bit -n = Value at POR bit 7
STATUS: STATUS REGISTER
R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC(1) R/W-x C(1) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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PIC12F635/PIC16F636/639
2.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting the PSA bit of the OPTION register to `1'. See Section 5.1.3 "Software Programmable Prescaler". The OPTION register is a readable and writable register which contains various control bits to configure: * * * * TMR0/WDT prescaler External RA2/INT interrupt TMR0 Weak pull-up/pull-downs on PORTA
REGISTER 2-2:
R/W-1 RAPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin T0CS: Timer0 Clock Source Select bit 1 = Transition on RA2/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
(c) 2007 Microchip Technology Inc.
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2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts.
REGISTER 2-3:
R/W-0 GIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RAIE(1,3) R/W-0 T0IF(2) R/W-0 INTF R/W-x RAIF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt INTE: RA2/INT External Interrupt Enable bit 1 = Enables the RA2/INT external interrupt 0 = Disables the RA2/INT external interrupt RAIE: PORTA Change Interrupt Enable bit(1,3) 1 = Enables the PORTA change interrupt 0 = Disables the PORTA change interrupt T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RA2/INT External Interrupt Flag bit 1 = The RA2/INT external interrupt occurred (must be cleared in software) 0 = The RA2/INT external interrupt did not occur RAIF: PORTA Change Interrupt Flag bit 1 = When at least one of the PORTA general purpose I/O pins changed state (must be cleared in software) 0 = None of the PORTA general purpose I/O pins have changed state IOCA register must also be enabled. T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. Includes ULPWU interrupt.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2: 3:
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2.2.2.4 PIE1 Register
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 2-4.
REGISTER 2-4:
R/W-0 EEIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 LVDIE R/W-0 CRIE R/W-0 C2IE
(1)
R/W-0 C1IE
R/W-0 OSFIE
U-0 --
R/W-0 TMR1IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enables the LVD interrupt 0 = Disables the LVD interrupt CRIE: Cryptographic Interrupt Enable bit 1 = Enables the cryptographic interrupt 0 = Disables the cryptographic interrupt C2IE: Comparator 2 Interrupt Enable bit(1) 1 = Enables the Comparator 2 interrupt 0 = Disables the Comparator 2 interrupt C1IE: Comparator 1 Interrupt Enable bit 1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt Unimplemented: Read as `0' TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt PIC16F636/639 only.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1 bit 0
Note 1:
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2.2.2.5 PIR1 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 2-5.
REGISTER 2-5:
R/W-0 EEIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0 LVDIF R/W-0 CRIF R/W-0 C2IF(1) R/W-0 C1IF R/W-0 OSFIF U-0 -- R/W-0 TMR1IF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEIF: EE Write Complete Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = The supply voltage has crossed selected LVD voltage (must be cleared in software) 0 = The supply voltage has not crossed selected LVD voltage CRIF: Cryptographic Interrupt Flag bit 1 = The Cryptographic module has completed an operation (must be cleared in software) 0 = The Cryptographic module has not completed an operation or is Idle C2IF: Comparator 2 Interrupt Flag bit(1) 1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed C1IF: Comparator 1 Interrupt Flag bit 1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed INTOSC (must be cleared in software) 0 = System clock operating Unimplemented: Read as `0' TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 rolled over (must be cleared in software) 0 = Timer1 has not rolled over PIC16F636/639 only.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1 bit 0
Note 1:
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2.2.2.6 PCON Register
The Power Control (PCON) register (see Table 12-3) contains flag bits to differentiate between a: * * * * * Power-on Reset (POR) Wake-up Reset (WUR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset
The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR. The PCON register bits are shown in Register 2-6.
REGISTER 2-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5
PCON: POWER CONTROL REGISTER
U-0 -- R/W-0 ULPWUE R/W-1 SBOREN(1) R/W-x WUR U-0 -- R/W-0 POR R/W-x BOR bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ULPWUE: Ultra Low-Power Wake-up Enable bit 1 = Ultra low-power wake-up enabled 0 = Ultra low-power wake-up disabled SBOREN: Software BOR Enable bit(1) 1 = BOR enabled 0 = BOR disabled WUR: Wake-up Reset Status bit 1 = No Wake-up Reset occurred 0 = A Wake-up Reset occurred (must be set in software after a Power-on Reset occurs) Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.
bit 4
bit 3
bit 2 bit 1
bit 0
Note 1:
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2.3 PCL and PCLATH
2.3.2 STACK
The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC12F635/PIC16F636/639 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.
FIGURE 2-5:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0 Instruction with PCL as Destination ALU Result
PCH 12 PC 5
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode<10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
2.4
Indirect Addressing, INDF and FSR Registers
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit of the STATUS register, as shown in Figure 2-6. A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1.
2.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 5 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program branch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table. For more information refer to Application Note AN556, "Implementing a Table Read" (DS00556).
EXAMPLE 2-1:
MOVLW MOVWF CLRF INCF BTFSS GOTO
INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;INC POINTER ;all done? ;no clear next ;yes continue
NEXT
CONTINUE
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FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639
Indirect Addressing 0 IRP 7 File Select Register 0
Direct Addressing RP1 RP0 6 From Opcode
Bank Select
Location Select 00 00h 01 10 11
Bank Select 180h
Location Select
Data Memory
7Fh Bank 0 Bank 1 Bank 2 Bank 3
1FFh
Note: For memory map detail, see Figure 2-2.
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NOTES:
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3.0
3.1
OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)
Overview
The Oscillator module can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. EC - External clock with I/O on OSC2/CLKOUT. LP - 32 kHz Low-Power Crystal mode. XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode. HS - High Gain Crystal or Ceramic Resonator mode. RC - External Resistor-Capacitor (RC) with FOSC/4 output on OSC2/CLKOUT. RCIO - External Resistor-Capacitor (RC) with I/O on OSC2/CLKOUT. INTOSC - Internal oscillator with FOSC/4 output on OSC2 and I/O on OSC1/CLKIN. INTOSCIO - Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT.
The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the Oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal via software. * Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator.
Clock Source modes are configured by the FOSC<2:0> bits in the Configuration Word register (CONFIG). The internal clock can be generated from two internal oscillators. The HFINTOSC is a calibrated high-frequency oscillator. The LFINTOSC is an uncalibrated low-frequency oscillator.
FIGURE 3-1:
PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0> (Configuration Word Register) SCS<0> (OSCCON Register)
External Oscillator OSC2 Sleep OSC1
LP, XT, HS, RC, RCIO, EC MUX INTOSC
IRCF<2:0> (OSCCON Register) 8 MHz Internal Oscillator 4 MHz 2 MHz Postscaler 101 100 500 kHz 250 kHz 125 kHz LFINTOSC 31 kHz 31 kHz 011 010 001 000 MUX 1 MHz HFINTOSC 8 MHz 111 110
System Clock (CPU and Peripherals)
Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
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3.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: * Frequency selection bits (IRCF) * Frequency Status bits (HTS, LTS) * System clock control bits (OSTS, SCS)
REGISTER 3-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 R-1 OSTS(1) R-0 HTS R-0 LTS R/W-0 SCS bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8 MHz 110 = 4 MHz (default) 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (LFINTOSC) OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Device is running from the external clock defined by FOSC<2:0> of the Configuration Word 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC) HTS: HFINTOSC Status bit (High Frequency - 8 MHz to 125 kHz) 1 = HFINTOSC is stable 0 = HFINTOSC is not stable LTS: LFINTOSC Stable bit (Low Frequency - 31 kHz) 1 = LFINTOSC is stable 0 = LFINTOSC is not stable SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> of the Configuration Word Bit resets to `0' with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled.
bit 3
bit 2
bit 1
bit 0
Note 1:
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3.3 Clock Source Modes 3.4
3.4.1
External Clock Modes
OSCILLATOR START-UP TIMER (OST)
Clock Source modes can be classified as external or internal. * External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. * Internal clock sources are contained internally within the Oscillator module. The Oscillator module has two internal oscillators: the 8 MHz High-Frequency Internal Oscillator (HFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bit of the OSCCON register. See Section 3.6 "Clock Switching" for additional information.
If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the Oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 3-1. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 3.7 "Two-Speed Clock Start-up Mode").
TABLE 3-1:
OSCILLATOR DELAY EXAMPLES
Switch To LFINTOSC HFINTOSC EC, RC EC, RC LP, XT, HS HFINTOSC Frequency 31 kHz 125 kHz to 8 MHz DC - 20 MHz DC - 20 MHz 32 kHz to 20 MHz 125 kHz to 8 MHz Oscillator Delay Oscillator Warm-Up Delay (TWARM) 2 instruction cycles 1 cycle of each 1024 Clock Cycles (OST) 1 s (approx.)
Switch From Sleep/POR Sleep/POR LFINTOSC (31 kHz) Sleep/POR LFINTOSC (31 kHz)
3.4.2
EC MODE
FIGURE 3-2:
The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 3-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC(R) MCU I/O OSC2/CLKOUT(1)
Clock from Ext. System
Note 1:
Alternate pin functions are listed in the Section 1.0 "Device Overview".
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3.4.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 3-3 and Figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949)
FIGURE 3-4:
CERAMIC RESONATOR OPERATION (XT OR HS MODE)
PIC(R) MCU
OSC1/CLKIN
FIGURE 3-3:
QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE)
PIC(R) MCU
OSC1/CLKIN C1
To Internal Logic RP(3) RF(2) Sleep
C1 Quartz Crystal
To Internal Logic RF(2) Sleep C2 Ceramic RS(1) Resonator OSC2/CLKOUT
C2
RS(1)
OSC2/CLKOUT
Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M). 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation.
Note 1: 2:
A series resistor (RS) may be required for quartz crystals with low drive level. The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M).
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3.4.4 EXTERNAL RC MODES
3.5
Internal Clock Modes
The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the external RC mode connections.
The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 3-2). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz.
2.
FIGURE 3-5:
VDD REXT
EXTERNAL RC MODES
PIC(R) MCU
The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register. The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit of the OSCCON register. See Section 3.6 "Clock Switching" for more information.
OSC1/CLKIN CEXT VSS FOSC/4 or I/O(2) OSC2/CLKOUT(1)
Internal Clock
3.5.1
INTOSC AND INTOSCIO MODES
Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: 2: Alternate pin functions are listed in the Section 1.0 "Device Overview". Output depends upon RC or RCIO clock mode.
The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section 12.0 "Special Features of the CPU" for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O.
In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: * threshold voltage variation * component tolerances * packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used.
3.5.2
HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 3-2). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). One of seven frequencies can be selected via software using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 "Frequency Select Bits (IRCF)" for more information. The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz by setting the IRCF<2:0> bits of the OSCCON register 000. Then, set the System Clock Source (SCS) bit of the OSCCON register to `1' or enable Two-Speed Start-up by setting the IESO bit in the Configuration Word register (CONFIG) to `1'. The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not.
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3.5.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-2). The default value of the OSCTUNE register is `0'. The value is a 5-bit two's complement number. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.
REGISTER 3-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 -- U-0 -- R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = * * * 00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 = * * * 10000 = Minimum frequency
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3.5.3 LFINTOSC 3.5.5
The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 "Frequency Select Bits (IRCF)" for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<2:0> bits of the OSCCON register = 000) as the system clock source (SCS bit of the OSCCON register = 1), or when any of the following are enabled: * Two-Speed Start-up IESO bit of the Configuration Word register = 1 and IRCF<2:0> bits of the OSCCON register = 000 * Power-up Timer (PWRT) * Watchdog Timer (WDT) * Fail-Safe Clock Monitor (FSCM) The LF Internal Oscillator (LTS) bit of the OSCCON register indicates whether the LFINTOSC is stable or not.
HF AND LF INTOSC CLOCK SWITCH TIMING
When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 3-6). If this is the case, there is a delay after the IRCF<2:0> bits of the OSCCON register are modified before the frequency selection takes place. The LTS and HTS bits of the OSCCON register will reflect the current active status of the LFINTOSC and HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. 2. 3. 4. 5. IRCF<2:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. CLKOUT is held low and the clock switch circuitry waits for a rising edge in the new clock. CLKOUT is now connected with the new clock. LTS and HTS bits of the OSCCON register are updated as required. Clock switch is complete.
6.
See Figure 3-1 for more details. If the internal oscillator speed selected is between 8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and new frequencies are derived from the HFINTOSC via the postscaler and multiplexer. Start-up delay specifications are located in the A/C Specifications (Oscillator Module) in Section 15.0 "Electrical Specifications".
3.5.4
FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register select the frequency output of the internal oscillators. One of eight frequencies can be selected via software: * * * * * * * * 8 MHz 4 MHz (Default after Reset) 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to `110' and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency.
(c) 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639
FIGURE 3-6:
LF(1) HF HFINTOSC HFINTOSC
Start-up Time 2-cycle Sync Running
INTERNAL OSCILLATOR SWITCH TIMING
LFINTOSC (FSCM and WDT disabled)
LFINTOSC IRCF <2:0> System Clock Note 1: When going from LF to HF. 0 =0
HFINTOSC HFINTOSC
LFINTOSC (Either FSCM or WDT enabled)
2-cycle Sync
Running
LFINTOSC IRCF <2:0> System Clock
0
=0
LFINTOSC LFINTOSC
HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
Start-up Time 2-cycle Sync
Running
HFINTOSC IRCF <2:0> System Clock =0
0
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PIC12F635/PIC16F636/639
3.6 Clock Switching
The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit of the OSCCON register. When the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 "Oscillator Start-up Timer (OST)"). The OST will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit of the OSCCON register is set, program execution switches to the external oscillator.
3.6.1
SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit of the OSCCON register selects the system clock source that is used for the CPU and peripherals. * When the SCS bit of the OSCCON register = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in the Configuration Word register (CONFIG). * When the SCS bit of the OSCCON register = 1, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<2:0> bits of the OSCCON register. After a Reset, the SCS bit of the OSCCON register is always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bit of the OSCCON register. The user can monitor the OSTS bit of the OSCCON register to determine the current system clock source.
3.7.1
TWO-SPEED START-UP MODE CONFIGURATION
Two-Speed Start-up mode is configured by the following settings: * IESO (of the Configuration Word register) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). * SCS (of the OSCCON register) = 0. * FOSC<2:0> bits in the Configuration Word register (CONFIG) configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or * Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.
3.6.2
OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of the OSCCON register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes.
3.7.2
1. 2.
TWO-SPEED START-UP SEQUENCE
3.7
Two-Speed Clock Start-up Mode
3. 4. 5. 6. 7.
Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear.
Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<2:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
(c) 2007 Microchip Technology Inc.
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3.7.3 CHECKING TWO-SPEED CLOCK STATUS
Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator.
FIGURE 3-7:
TWO-SPEED START-UP
HFINTOSC T TOST OSC1 0 1 1022 1023
OSC2 Program Counter PC - N PC PC + 1
System Clock
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3.8 Fail-Safe Clock Monitor
3.8.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG). The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO). The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register. When the SCS bit is toggled, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.
FIGURE 3-8:
FSCM BLOCK DIAGRAM
Clock Monitor Latch S Q
3.8.4
RESET OR WAKE-UP FROM SLEEP
External Clock
LFINTOSC Oscillator 31 kHz (~32 s)
/ 64 488 Hz (~2 ms)
R
Q
The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Note:
Clock Failure Detected
Sample Clock
3.8.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 3-8. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the primary clock goes low.
Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock switchover has successfully completed.
3.8.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR1 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE1 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.
(c) 2007 Microchip Technology Inc.
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FIGURE 3-9:
Sample Clock System Clock Output Clock Monitor Output (Q) Failure Detected OSFIF Oscillator Failure
FSCM TIMING DIAGRAM
Test Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
TABLE 3-2:
Name CONFIG(2) INTCON OSCCON OSCTUNE PIE1 PIR1 Legend: Note 1: 2:
3:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Bit 7 CPD GIE -- -- EEIE EEIF Bit 6 CP PEIE IRCF2 -- LVDIE LVDIF Bit 5 MCLRE T0IE IRCF1 -- CRIE CRIF Bit 4 PWRTE INTE IRCF0 TUN4 C2IE(3) C2IF(3) Bit 3 WDTE RAIE OSTS TUN3 C1IE C1IF Bit 2 FOSC2 T0IF HTS TUN2 OSFIE OSFIF Bit 1 FOSC1 INTF LTS TUN1 -- -- Bit 0 FOSC0 RAIF SCS TUN0 TMR1IE TMR1IF Value on POR, BOR -- 0000 000x -110 x000 ---0 0000 000- 00-0 000- 00-0 Value on all other Resets(1) -- 0000 000x -110 x000 ---u uuuu 000- 00-0 000- 00-0
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by oscillators. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. See Configuration Word register (CONFIG) for operation of all register bits.
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4.0 I/O PORTS
4.2 Additional Pin Functions
There are as many as twelve general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Every PORTA pin on the PIC12F635/PIC16F636/639 has an interrupt-on-change option and a weak pull-up/pull-down option. RA0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions.
4.2.1
WEAK PULL-UP/PULL-DOWN
4.1
PORTA and the TRISA Registers
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 4-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as `1'. Example 4-1 shows how to initialize PORTA. Note: PORTA = GPIO TRISA = TRISIO Reading the PORTA register (Register 4-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. RA3 reads `0' when MCLRE = 1. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read `0'. Note: The CMCON0 register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
Each of the PORTA pins, except RA3, has an internal weak pull-up and pull-down. The WDA bits select either a pull-up or pull-down for an individual port bit. Individual control bits can turn on the pull-up or pull-down. These pull-ups/pull-downs are automatically turned off when the port pin is configured as an output, as an alternate function or on a Power-on Reset, setting the RAPU bit of the OPTION register. A weak pull-up on RA3 is enabled when configured as MCLR in the Configuration Word register and disabled when high voltage is detected, to reduce current consumption through RA3, while in Programming mode. Note: PORTA = GPIO TRISA = TRISIO
EXAMPLE 4-1:
BANKSEL PORTA CLRF PORTA MOVLW 07h MOVWF CMCON0 BSF STATUS,RP0 BCF STATUS,RP1 MOVLW 0Ch MOVWF TRISA
INITIALIZING PORTA
; ;Init PORTA ;Set RA<2:0> to ;digital I/O ;Bank 1 ; ;Set RA<3:2> as inputs ;and set RA<5:4,1:0> ;as outputs
(c) 2007 Microchip Technology Inc.
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REGISTER 4-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PORTA: PORTA REGISTER
U-0 -- R/W-x RA5 R/W-x RA4 R-x RA3 R/W-x RA2 R/W-x RA1 R/W-x RA0 bit 0
Unimplemented: Read as `0' RA<5:0>: PORTA I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL
REGISTER 4-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
TRISA: PORTA TRI-STATE REGISTER
U-0 -- R/W-1 TRISA5 R/W-1 TRISA4 R-1 TRISA3 R/W-1 TRISA2 R/W-1 TRISA1 R/W-1 TRISA0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TRISA<5:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output TRISA<3> always reads `1'. TRISA<5:4> always reads `1' in XT, HS and LP Oscillator modes.
Note 1: 2:
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REGISTER 4-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
WDA: WEAK PULL-UP/PULL-DOWN DIRECTION REGISTER
U-0 -- R/W-1 WDA5 R/W-1 WDA4 U-0 -- R/W-1 WDA2 R/W-1 WDA1 R/W-1 WDA0 bit 0
Unimplemented: Read as `0' WDA<5:4>: Pull-up/Pull-down Selection bits 1 = Pull-up selected 0 = Pull-down selected Unimplemented: Read as `0' WDA<2:0>: Pull-up/Pull-down Selection bits 1 = Pull-up selected 0 = Pull-down selected The weak pull-up/pull-down device is enabled only when the global RAPU bit is enabled, the pin is in Input mode (TRIS = 1), the individual WDA bit is enabled (WDA = 1) and the pin is not configured as an analog input or clock function. RA3 pull-up is enabled when the pin is configured as MCLR in the Configuration Word register and the device is not in Programming mode.
bit 3 bit 2-0
Note 1: 2:
REGISTER 4-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4
WPUDA: WEAK PULL-UP/PULL-DOWN ENABLE REGISTER
U-0 -- R/W-1 WPUDA5(3) R/W-1 WPUDA4(3) U-0 -- R/W-1 WPUDA2 R/W-1 WPUDA1 R/W-1 WPUDA0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' WPUDA<5:4>: Pull-up/Pull-down Direction Selection bits(3) 1 = Pull-up/pull-down enabled 0 = Pull-up/pull-down disabled Unimplemented: Read as `0' WPUDA<2:0>: Pull-up/Pull-down Direction Selection bits 1 = Pull-up/pull-down enabled 0 = Pull-up/pull-down disabled The weak pull-up/pull-down direction device is enabled only when the global RAPU bit is enabled, the pin is in Input mode (TRIS = 1), the individual WPUDA bit is enabled (WPUDA = 1) and the pin is not configured as an analog input or clock function. RA3 pull-up is enabled when the pin is configured as MCLR in the Configuration Word register and the device is not in Programming mode. WPUDA5 bit can be written if INTOSC is enabled and T1OSC is disabled; otherwise, the bit can not be written and reads as `1'. WPUDA4 bit can be written if not configured as OSC2; otherwise, the bit can not be written and reads as `1'
bit 3 bit 2-0
Note 1:
2: 3:
(c) 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639
4.2.2 INTERRUPT-ON-CHANGE
Each of the PORTA pins is individually configurable as an interrupt-on-change pin. Control bits, IOCAx, enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTA. The `mismatch' outputs of the last read are OR'd together to set the PORTA Change Interrupt Flag bit (RAIF) in the INTCON register. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) b) Any read or write of PORTA. This will end the mismatch condition, then Clear the flag bit RAIF. A mismatch condition will continue to set flag bit RAIF. Reading PORTA will end the mismatch condition and allow flag bit RAIF to be cleared. The latch holding the last read value is not affected by a MCLR nor BOR Reset. After these Resets, the RAIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.
REGISTER 4-5:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0 -- R/W-0 IOCA5(2) R/W-0 IOCA4(2) R/W-0 IOCA3(3) R/W-0 IOCA2 R/W-0 IOCA1 R/W-0 IOCA0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' IOCA<5:0>: Interrupt-on-Change PORTA Control bits(2,3) 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads `0' in XT, HS and LP Oscillator modes. 3: IOCA<3> is ignored when WUR is enabled and the device is in Sleep mode.
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4.2.3 ULTRA LOW-POWER WAKE-UP EXAMPLE 4-2:
BANKSEL BSF MOVLW MOVWF BANKSEL BCF CALL BSF BSF BSF MOVLW MOVWF SLEEP NOP
The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change on RA0 without excess current consumption. The mode is selected by setting the ULPWUE bit of the PCON register. This enables a small current sink which can be used to discharge a capacitor on RA0. To use this feature, the RA0 pin is configured to output `1' to charge the capacitor, interrupt-on-change for RA0 is enabled and RA0 is configured as an input. The ULPWUE bit is set to begin the discharge and a SLEEP instruction is performed. When the voltage on RA0 drops below VIL, an interrupt will be generated which will cause the device to wake-up. Depending on the state of the GIE bit of the INTCON register, the device will either jump to the interrupt vector (0004h) or execute the next instruction when the interrupt event occurs. See Section 4.2.2 "Interrupt-on-Change" and Section 12.9.3 "PORTA Interrupt" for more information. This feature provides a low-power technique for periodically waking up the device from Sleep. The time-out is dependent on the discharge time of the RC circuit on RA0. See Example 4-2 for initializing the Ultra Low Power Wake-up module. The series resistor provides overcurrent protection for the RA0 pin and can allow for software calibration of the time-out (see Figure 4-1). A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired interrupt delay. This technique will compensate for the affects of temperature, voltage and component accuracy. The Ultra Low-Power Wake-up peripheral can also be configured as a simple Programmable Low-Voltage Detect or temperature sensor. Note: For more information, refer to the Application Note AN879, "Using the Microchip Ultra Low-Power Wake-up Module" (DS00879).
ULTRA LOW-POWER WAKE-UP INITIALIZATION
; ;Set RA0 data latch ;Turn off ; comparators ; ;Output high to ; charge capacitor ;Enable ULP Wake-up ;Select RA0 IOC ;RA0 to input ;Enable interrupt ; and clear flag ;Wait for IOC ;
PORTA PORTA,0 H'7' CMCON0 TRISA TRISA,0 CapDelay PCON,ULPWUE IOCA,0 TRISA,0 B'10001000' INTCON
(c) 2007 Microchip Technology Inc.
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4.2.4 PIN DESCRIPTIONS AND DIAGRAMS 4.2.4.1 RA0/C1IN+/ICSPDAT/ULPWU
Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, such as the comparator, refer to the appropriate section in this data sheet. Figure 4-2 shows the diagram for this pin. The RA0 pin is configurable to function as one of the following: * * * * a general purpose I/O an analog input to the comparator In-Circuit Serial ProgrammingTM data an analog input for the Ultra Low-Power Wake-up
FIGURE 4-1:
BLOCK DIAGRAM OF RA0
Analog Input Mode(1)
Data Bus WR WPUDA RD WPUDA
VDD D Q Weak CK Q RAPU Weak
D WR WDA RD WDA D WR PORTA
Q
CK Q VDD
Q I/O pin
CK Q - + D Q IULP 0 1 VSS ULPWUE
VSS VT
WR TRISA RD TRISA RD PORTA
CK Q
Analog Input Mode(1)
D WR IOCA RD IOCA
Q Q D EN Q1
CK Q
Interrupt-onChange
Q
D EN
RD PORTA
Note
1:
Comparator mode determines Analog Input mode.
DS41232D-page 52
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4.2.4.2 RA1/C1IN-/VREF/ICSPCLK 4.2.4.3 RA2/T0CKI/INT/C1OUT
Figure 4-2 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: * a general purpose I/O * an analog input to the comparator * In-Circuit Serial ProgrammingTM clock Figure 4-3 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: * * * * a general purpose I/O the clock input for Timer0 an external edge-triggered interrupt a digital output from the comparator
FIGURE 4-2:
Data Bus WR WPUDA RD WPUDA D WR WDA RD WDA D WR PORTA Q Q D Q
BLOCK DIAGRAM OF RA1
Analog Input Mode(1) VDD
FIGURE 4-3:
Data Bus WR WPUDA RD WPUDA D WR WDA RD WDA VDD D Q Q Q D Q
BLOCK DIAGRAM OF RA2
CK Q RAPU
VDD Weak CK Q RAPU Weak Weak
Weak
CK Q
VSS
CK Q
VSS
C1OUT Enable C1OUT 1 0
VDD
CK Q I/O pin D Q
WR PORTA
CK
I/O pin
WR TRISA RD TRISA RD PORTA
D CK Q Analog Input Mode(1) VSS WR TRISA RD TRISA RD PORTA Q D EN Q1 WR IOCA RD IOCA D CK CK
Q Q VSS
D WR IOCA RD IOCA
Q
CK Q
Q Q Q EN Q1 D
Q
D EN
Q
D EN
Interrupt-onchange RD PORTA To Comparator
Interrupt-onchange
RD PORTA
To Timer0 Note 1: Comparator mode determines Analog Input mode. To INT
(c) 2007 Microchip Technology Inc.
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4.2.4.4 RA3/MCLR/VPP
Figure 4-4 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: * a general purpose input * as Master Clear Reset with weak pull-up * a high-voltage detect for Program mode entry
FIGURE 4-4:
BLOCK DIAGRAM OF RA3
VDD MCLRE Program Mode Weak
HV Detect Reset MCLRE
Data Bus Input pin MCLRE VSS D WR IOCA RD IOCA Q D EN CK Q Q Q EN Q1 D
RD TRISA RD PORTA
VSS
RD PORTA
Interrupt-onchange
WURE Sleep
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4.2.4.5 RA4/T1G/OSC2/CLKOUT 4.2.4.6 RA5/T1CKI/OSC1/CLKIN
Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: * * * * a general purpose I/O a Timer1 gate input a crystal/resonator connection a clock output Figure 4-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: * * * * a general purpose I/O a Timer1 clock input a crystal/resonator connection a clock input
FIGURE 4-5:
Data Bus WR WPUDA RD WPUDA D WR WDA RD WDA Q
BLOCK DIAGRAM OF RA4
FIGURE 4-6:
Data Bus
BLOCK DIAGRAM OF RA5
D
Q
CLK(1) Modes
D
Q
VDD Weak WR WPUDA RD WPUDA D VSS WR WDA RD WDA VDD D WR PORTA I/O pin D VSS WR TRISA RD TRISA RD PORTA D Q CK Q Q CK Q Q Q CK Q
CLK(1) Modes
VDD Weak
CK Q RAPU
RAPU Weak
Weak
CK Q Oscillator Circuit OSC1 CLKOUT Enable D Q Q CLKOUT Enable D Q Q INTOSC/ RC/EC(2) CLKOUT Enable XTAL FOSC/4 1 0
CK Q
VSS
Oscillator Circuit OSC2 VDD
WR PORTA
CK
I/O pin
VSS INTOSC Mode
(2)
WR TRISA RD TRISA RD PORTA
CK
D WR IOCA RD IOCA CK
Q Q Q EN Q D EN Q1 D
WR IOCA RD IOCA
CK
Q Q
D EN Q1
Q
D EN
Interrupt-onchange
Interrupt-onchange
RD PORTA RD PORTA T1G To Timer1 Note 1: 2: Oscillator modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. With CLKOUT option. Note T1G To Timer1 1: 2: Oscillator modes are XT, HS, LP and LPTMR1. When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed.
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TABLE 4-1:
Name PORTA INTCON TMR1L TMR1H T1CON CMCON1 CMCON0 OPTION_REG TRISA WPUDA IOCA WDA Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- GIE Bit 6 -- PEIE Bit 5 RA5 T0IE Bit 4 RA4 INTE Bit 3 RA3 RAIE Bit 2 RA2 T0IF Bit 1 RA1 INTF Bit 0 RA0 RAIF Value on POR, BOR, WUR --xx xx00 0000 000x xxxx xxxx xxxx xxxx TMR1CS T1GSS CM1 PS1 TRISA1 WPUDA1 IOCA1 WDA1 TMR1ON CxSYNC CM0 PS0 TRISA0 WPUDA0 IOCA0 WDA0 0000 0000 ---- --10 0000 0000 1111 1111 --11 1111 --11 -111 --00 0000 --11 -111 Value on all other Resets --uu uu00 0000 000x uuuu uuuu uuuu uuuu uuuu uuuu ---- --10 0000 0000 1111 1111 --11 1111 --11 -111 --00 0000 --11 -111
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register T1GINV -- C2OUT RAPU -- -- -- -- TMR1GE -- C1OUT INTEDG -- -- -- -- T1CKPS1 -- C2INV T0CS TRISA5 WPUDA5 IOCA5 WDA5 T1CKPS0 -- C1INV T0SE TRISA4 WPUDA4 IOCA4 WDA4 T1OSCEN -- CIS PSA TRISA3 -- IOCA3 -- T1SYNC -- CM2 PS2 TRISA2 WPUDA2 IOCA2 WDA2
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
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4.3 PORTC
EXAMPLE 4-3:
BANKSEL CLRF MOVLW MOVWF BANKSEL MOVLW MOVWF PORTC PORTC 07h CMCON0 TRISC 0Ch TRISC
INITIALIZING PORTC
; ;Init PORTC ;Set RC<4,1:0> to ;digital I/O ; ;Set RC<3:2> as inputs ;and set RC<5:4,1:0> ;as outputs
PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to comparator. For specific information about individual functions, refer to the appropriate section in this data sheet. Note: The CMCON0 register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
REGISTER 4-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
PORTC: PORTC REGISTER
U-0 -- R/W-x RC5 R/W-x RC4 R/W-x RC3 R/W-x RC2 R/W-0 RC1 R/W-0 RC0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RC<5:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL
REGISTER 4-7:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
TRISC: PORTC TRI-STATE REGISTER
U-0 -- R/W-1 TRISC5 R/W-1 TRISC4 R-1 TRISC3 R/W-1 TRISC2 R/W-1 TRISC1 R/W-1 TRISC0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TRISC<5:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output
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4.3.1 RC0/C2IN+ FIGURE 4-7:
Data Bus
Figure 4-7 shows the diagram for this pin. The RC0 pin is configurable to function as one of the following: * a general purpose I/O * an analog input to the comparator
BLOCK DIAGRAM OF RC0 AND RC1
D WR PORTC CK
Q Q
VDD
4.3.2
RC1/C2IN-
Figure 4-7 shows the diagram for this pin. The RC1 pin is configurable to function as one of the following: * a general purpose I/O * an analog input to the comparator
WR TRISC RD TRISC RD PORTC
I/O pin D CK Q Q Analog Input Mode VSS
4.3.3
RC2
Figure 4-8 shows the diagram for this pin. The RC2 pin is configurable to function as a general purpose I/O.
4.3.4
RC3
Figure 4-8 shows the diagram for this pin. The RC3 pin is configurable to function as a general purpose I/O.
To Comparators
4.3.5
RC5
Figure 4-8 shows the diagram for this pin. The RC5 pin is configurable to function as a general purpose I/O.
FIGURE 4-8:
BLOCK DIAGRAM OF RC2, RC3 AND RC5
Data Bus VDD
D WR PORTC CK
Q Q
I/O pin D WR TRISC RD TRISC RD PORTC CK Q Q VSS
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4.3.6 RC4/C2OUT
Figure 4-9 shows the diagram for this pin. The RC4 pin is configurable to function as one of the following: * a general purpose I/O * a digital output from the comparator
FIGURE 4-9:
C2OUT Enable C2OUT
BLOCK DIAGRAM OF RC4
Data Bus VDD
D WR PORTC
Q 1 0
CK Q
I/O pin
D WR TRISC RD TRISC RD PORTC
Q VSS
CK Q
TABLE 4-2:
Name PORTC CMCON0 TRISC Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 -- C2OUT -- Bit 6 -- C1OUT -- Bit 5 RC5 C2INV TRISC5 Bit 4 RC4 C1INV TRISC4 Bit 3 RC3 CIS TRISC3 Bit 2 RC2 CM2 TRISC2 Bit 1 RC1 CM1 TRISC1 Bit 0 RC0 CM0 TRISC0 Value on POR, BOR, WUR --xx xx00 0000 0000 --11 1111 Value on all other Resets --uu uu00 0000 0000 --11 1111
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
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NOTES:
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5.0 TIMER0 MODULE
5.1 Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the following features: * * * * * 8-bit timer/counter register (TMR0) 8-bit prescaler (shared with Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter.
5.1.1
8-BIT TIMER MODE
When used as a timer, the Timer0 module will increment every instruction cycle (without prescaler). Timer mode is selected by clearing the T0CS bit of the OPTION register to `0'. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written.
Figure 5-1 is a block diagram of the Timer0 module.
5.1.2
8-BIT COUNTER MODE
When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to `1'.
FIGURE 5-1:
FOSC/4
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 1 1 T0CKI pin T0SE T0CS 1 8 0 0 8-bit Prescaler PSA Set Flag bit T0IF on Overflow Sync 2 TCY TMR0 8
WDTE SWDTEN
PSA
PS<2:0> 16-bit Prescaler 31 kHz INTOSC Watchdog Timer WDTPS<3:0>
Note 1: 2: 3: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. SWDTEN and WDTPS<3:0> are bits in the WDTCON register. WDTE bit is in the Configuration Word register.
1 WDT Time-out 0
16 PSA
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5.1.3 SOFTWARE PROGRAMMABLE PRESCALER
A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a `0'. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 5-2).
EXAMPLE 5-2:
CLRWDT
CHANGING PRESCALER (WDT TIMER0)
;Clear WDT and ;prescaler BANKSEL OPTION_REG ; MOVLW b'11110000' ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b'00000011' ;Set prescale to 1:16 MOVWF OPTION_REG ;
5.1.4
TIMER0 INTERRUPT
5.1.3.1
Switching Prescaler Between Timer0 and WDT Modules
Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register.. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep.
As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 5-1, must be executed.
5.1.5
USING TIMER0 WITH AN EXTERNAL CLOCK
EXAMPLE 5-1:
BANKSEL CLRWDT CLRF BANKSEL BSF CLRWDT MOVLW ANDWF IORLW MOVWF TMR0 TMR0
CHANGING PRESCALER (TIMER0 WDT)
; ;Clear WDT ;Clear TMR0 and ;prescaler ; ;Select WDT ; ; ;Mask prescaler ;bits ;Set WDT prescaler ;to 1:32
When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in the Section 15.0 "Electrical Specifications".
OPTION_REG OPTION_REG,PSA
b'11111000' OPTION_REG,W b'00000101' OPTION_REG
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REGISTER 5-1:
R/W-1 RAPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
BIT VALUE 000 001 010 011 100 101 110 111 TMR0 RATE 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT RATE 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
A dedicated 16-bit WDT postscaler is available. See Section 12.11 "Watchdog Timer (WDT)" for more information.
TABLE 5-1:
Name TMR0 INTCON OPTION_REG TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Timer0 Module Register GIE -- PEIE -- T0IE T0CS INTE T0SE RAIE PSA T0IF PS2 INTF PS1 RAIF PS0 RAPU INTEDG
xxxx xxxx uuuu uuuu 0000 000x 0000 000x 1111 1111 1111 1111
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
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6.0 TIMER1 MODULE WITH GATE CONTROL
The Timer1 module is a 16-bit timer/counter with the following features: 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 3-bit prescaler Optional LP oscillator Synchronous or asynchronous operation Timer1 gate (count enable) via comparator or T1G pin * Interrupt on overflow * Wake-up on overflow (external clock, Asynchronous mode only) * Comparator output synchronization to Timer1 clock Figure 6-1 is a block diagram of the Timer1 module. * * * * * *
6.1
Timer1 Operation
The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter.
6.2
Clock Source Selection
The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source is supplied externally.
Clock Source FOSC/4 T1CKI pin T1LPOSC
T1OSCEN x x 1
FOSC Mode xxx LP or INTOSCIO
T1CS x 1
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FIGURE 6-1: TIMER1 BLOCK DIAGRAM
TMR1GE TMR1ON Set flag bit TMR1IF on Overflow To C2 Comparator Module Timer1 Clock EN 0 Synchronized clock input T1GINV
TMR1(2) TMR1H TMR1L
1
Oscillator
(1)
T1SYNC 1 Prescaler 1, 2, 4, 8 0 Synchronize(3) det
OSC1/T1CKI
OSC2/T1G TMR1CS
2 T1CKPS<1:0> 1
INTOSC Without CLKOUT T1OSCEN
FOSC FOSC/4 Internal Clock
1 0 T1ACS
CxOUT
0 T1GSS
Note 1: 2: 3:
ST Buffer is low power type when using LP osc, or high speed type when using T1CKI. Timer1 register increments on rising edge. Synchronize does not operate while in Sleep.
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6.2.1 INTERNAL CLOCK SOURCE
6.5
When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler.
Timer1 Operation in Asynchronous Counter Mode
6.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after one or more of the following conditions: * Timer1 is enabled after POR or BOR Reset * A write to TMR1H or TMR1L * T1CKI is high when Timer1 is disabled and when Timer1 is reenabled T1CKI is low. See Figure 6-2.
If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 6.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce a single spurious increment.
6.5.1
6.3
Timer1 Prescaler
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TTMR1L register pair.
6.4
Timer1 Oscillator
A low-power 32.768 kHz crystal oscillator is built-in between pins OSC1 (input) and OSC2 (amplifier output). The oscillator is enabled by setting the T1OSCEN control bit of the T1CON register. The oscillator will continue to run during Sleep. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator or when in LP oscillator mode. The user must provide a software time delay to ensure proper oscillator start-up. TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled. RA5 and RA4 bits read as `0' and TRISA5 and TRISA4 bits read as `1'. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.
6.6
Timer1 Gate
Timer1 gate source is software configurable to be the T1G pin or the output of Comparator 2. This allows the device to directly time external events using T1G or analog events using Comparator 2. See the CMCON1 register (Register 7-3) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Note: TMR1GE bit of the T1CON register must be set to use either T1G or C2OUT as the Timer1 gate source. See Register 7-3 for more information on selecting the Timer1 gate source.
Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active-high or active-low time between events.
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6.7 Timer1 Interrupt 6.9 Comparator Synchronization
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * Timer1 interrupt enable bit of the PIE1 register * PEIE bit of the INTCON register * GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. The same clock used to increment Timer1 can also be used to synchronize the comparator output. This feature is enabled in the Comparator module. When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. This ensures Timer1 does not miss an increment if the comparator changes. For more information, see Section 7.0 "Comparator Module".
6.8
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * TMR1ON bit of the T1CON register must be set * TMR1IE bit of the PIE1 register must be set * PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h).
FIGURE 6-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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6.10 Timer1 Control Register
The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module.
REGISTER 6-1:
R/W-0 T1GINV bit 7 Legend: R = Readable bit -n = Value at POR bit 7
(1)
T1CON: TIMER 1 CONTROL REGISTER
R/W-0 R/W-0
(2)
R/W-0 T1CKPS0
R/W-0 T1OSCEN
R/W-0 T1SYNC
R/W-0 TMR1CS
R/W-0 TMR1ON bit 0
TMR1GE
T1CKPS1
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if Timer1 gate is active 0 = Timer1 is on T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored. LP oscillator is disabled. T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 T1GINV bit inverts the Timer1 gate logic, regardless of source. TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CMCON1 register, as a Timer1 gate source.
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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TABLE 6-1:
Name
CMCON1 INTCON PIE1 PIR1 TMR1H TMR1L T1CON Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 6
-- PEIE LVDIE
Bit 7
-- GIE EEIE
Bit 5
-- T0IE CRIE
Bit 4
-- INTE C2IE(1)
Bit 3
-- RAIE C1IE
Bit 2
-- T0IF OSFIE
Bit 1
T1GSS INTF --
Bit 0
CMSYNC RAIF TMR1IE
Value on POR, BOR
---- --10 0000 000x 000- 00-0 000- 00-0 xxxx xxxx xxxx xxxx
Value on all other Resets
00-- --10 0000 000x 000- 00-0 000- 00-0 uuuu uuuu uuuu uuuu uuuu uuuu
EEIF
LVDIF
CRIF
C2IF(1)
C1IF
OSFIF
--
TMR1IF
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
0000 0000
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module. PIC16F636/639 only.
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NOTES:
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7.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution. The Analog Comparator module includes the following features: * Dual comparators (PIC16F636/639 only) * Multiple comparator configurations * Comparator(s) output is available internally/externally * Programmable output polarity * Interrupt-on-change * Wake-up from Sleep * Timer1 gate (count enable) * Output synchronization to Timer1 clock input * Programmable voltage reference comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. The PIC12F635 contains a single comparator as shown in Figure 7-2. The PIC16F636/639 devices contains two comparators as shown in Figure 7-3 and Figure 7-4. The comparators are not independently configurable.
FIGURE 7-1:
VIN+ VIN-
SINGLE COMPARATOR
+ - Output
VINVIN+
7.1
Comparator Overview
Output Note: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time.
A comparator is shown in Figure 7-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the
FIGURE 7-2:
MULTIPLEX
COMPARATOR OUTPUT BLOCK DIAGRAM (PIC12F635)
CMSYNC CINV 0 To COUT pin D Timer1 clock source(1) Q 1 To Timer1 Gate
(c) 2007 Microchip Technology Inc.
Port Pins
D Q1 EN
Q
To Data Bus
RD CMCON0 Set CMIF bit
D Q3*RD CMCON0 EN
Q
CL
Reset Note 1: 2: 3: Comparator output is latched on falling edge of Timer1 clock source. Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode.
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FIGURE 7-3: COMPARATOR C1 OUTPUT BLOCK DIAGRAM (PIC16F636/639)
MULTIPLEX
C1INV C1
FIGURE 7-4:
DS41232D-page 72
Port Pins Port Pins
To C1OUT pin
D Q1 EN
Q
To Data Bus
RD CMCON0 Set C1IF bit
D Q3*RD CMCON0 EN
Q
CL
Reset Note 1: 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode.
COMPARATOR C2 OUTPUT BLOCK DIAGRAM (PIC16F636/639)
C2SYNC C2INV C2 D Timer1 clock source(1) Q 0 To C2OUT pin 1 To Timer1 Gate MULTIPLEX Note 1: 2: 3:
D Q1 EN
Q
To Data Bus
RD CMCON0 Set C2IF bit
D Q3*RD CMCON0 EN
Q
CL
Reset
Comparator output is latched on falling edge of Timer1 clock source. Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode.
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
7.2 Analog Input Connection Considerations
Note 1: When reading a PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified.
A simplified circuit for an analog input is shown in Figure 7-5. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced.
FIGURE 7-5:
ANALOG INPUT MODEL
VDD Rs < 10K AIN VT 0.6V RIC To Comparator
VA
CPIN 5 pF
VT 0.6V
ILEAKAGE 500 nA
Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance = Source Impedance RS = Analog Voltage VA VT = Threshold Voltage
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PIC12F635/PIC16F636/639
7.3 Comparator Configuration
There are eight modes of operation for the comparator. The CM<2:0> bits of the CMCON0 register are used to select these modes as shown in Figures 7-6 and 7-7. I/O lines change as a function of the mode and are designed as follows: * Analog function (A): digital input buffer is disabled * Digital function (D): comparator digital output, overrides port function * Normal port function (I/O): independent of comparator The port pins denoted as "A" will read as a `0' regardless of the state of the I/O pin or the I/O control TRIS bit. Pins used as analog inputs should also have the corresponding TRIS bit set to `1' to disable the digital output driver. Pins denoted as "D" should have the corresponding TRIS bit set to `0' to enable the digital output driver. Note: Comparator interrupts should be disabled during a Comparator mode change to prevent unintended interrupts.
FIGURE 7-6:
CM<2:0> = 000
COMPARATOR I/O OPERATING MODES (PIC12F635)
Comparator w/o Output and with Internal Reference CM<2:0> = 100
CINOff
(1)
Comparator Reset (POR Default Value - low power)
CINCIN+
A A
A I/O COUT
CIN+
COUT (pin) I/O
COUT (pin) I/O From CVREF Module
Comparator with Output CM<2:0> = 001
Multiplexed Input with Internal Reference and Output CM<2:0> = 101
CINCOUT CIN+ A A CIS = 0 CIS = 1 COUT
CINCIN+
A A
COUT (pin) D
COUT (pin) D From CVREF Module
Comparator without Output CM<2:0> = 010
Multiplexed Input with Internal Reference CM<2:0> = 110
CINCIN+ COUT (pin)
A A I/O COUT
CINCIN+ COUT (pin)
A A I/O From CVREF Module CIS = 0 CIS = 1 COUT
Comparator with Output and Internal Reference CM<2:0> = 011
Comparator Off (Lowest power) CM<2:0> = 111
CINCIN+
A I/O COUT CINCIN+ From CVREF Module I/O I/O Off(1)
COUT (pin) D
COUT (pin) I/O
Legend: A = Analog Input, ports always reads `0' I/O = Normal port I/O Note 1: Reads as `0', unless CINV = 1.
CIS = Comparator Input Switch (CMCON0<3>) D = Comparator Digital Output
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FIGURE 7-7: COMPARATOR I/O OPERATING MODES (PIC16F636/639)
Two Independent Comparators CM<2:0> = 100 VINC1IN- A
C1IN+ C2INC2 Off
(1)
Comparators Reset (POR Default Value) CM<2:0> = 000 A VINC1INC1IN+ A C2INA
VIN+ VINVIN+
C1
Off(1)
A
VIN+ VINVIN+
C1
C1OUT
A A
C2IN+ A
C2IN+
C2
C2OUT
Three Inputs Multiplexed to Two Comparators CM<2:0> = 001
C1INC1IN+
A A
CIS = 0 CIS = 1
VINVIN+ VINVIN+
C2 C2OUT C1 C1OUT
One Independent Comparator CM<2:0> = 101 I/O VINC1INC1IN+
I/O
VIN+
C1
Off(1)
C2INC2IN+
A A
C2INC2IN+
A A
VINVIN+
C2 C2OUT
Four Inputs Multiplexed to Two Comparators CM<2:0> = 010
C1INC1IN+ C2INC2IN+
A A
CIS = 0 CIS = 1
VINVIN+ VINVIN+
C2 C2OUT C1 C1OUT
Two Common Reference Comparators with Outputs CM<2:0> = 110 A VINC1INVIN+
C1OUT(pin)
D A A D
C1
C1OUT
A A
CIS = 0 CIS = 1
C2INC2IN+ C2OUT(pin)
VINVIN+
C2 C2OUT
From CVREF Module
Two Common Reference Comparators CM<2:0> = 011 A VINC1INC1IN+
I/O
Comparators Off (Lowest Power) CM<2:0> = 111
C1INI/O
VINVIN+
C1 Off(1)
VIN+
C1
C1OUT
C1IN+ I/O
C2INC2IN+
A A
VINVIN+
C2 C2OUT
C2IN-
I/O
VINVIN+
C2 Off(1)
C2IN+ I/O
Legend: A = Analog Input, ports always reads `0' I/O = Normal port I/O Note 1: Reads as `0', unless CxINV = 1.
CIS = Comparator Input Switch (CMCON0<3>) D = Comparator Digital Output
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7.4 Comparator Control
7.4.3 COMPARATOR INPUT SWITCH
The CMCON0 register (Register 7-1) provides access to the following comparator features: * * * * Mode selection Output state Output polarity Input switch The inverting input of the comparators may be switched between two analog pins in the following modes: PIC12F635 * CM<2:0> = 101 * CM<2:0> = 110 PIC16F636/639 * CM<2:0> = 001 (Comparator C1 only) * CM<2:0> = 010 (Comparators C1 and C2) In the above modes, both pins remain in Analog mode regardless of which pin is selected as the input. The CIS bit of the CMCON0 register controls the comparator input switch.
7.4.1
COMPARATOR OUTPUT STATE
Each comparator state can always be read internally via the CxOUT bit of the CMCON0 register. The comparator state may also be directed to the CxOUT pin in the following modes: PIC12F635 * CM<2:0> = 001 * CM<2:0> = 011 * CM<2:0> = 101 PIC16F636/639 * CM<2:0> = 110 When one of the above modes is selected, the associated TRIS bit of the CxOUT pin must be cleared.
7.4.2
COMPARATOR OUTPUT POLARITY
Inverting the output of a comparator is functionally equivalent to swapping the comparator inputs. The polarity of a comparator output can be inverted by setting the CXINV bit of the CMCON0 register. Clearing CXINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 7-1.
TABLE 7-1:
OUTPUT STATE VS. INPUT CONDITIONS
CxINV 0 0 1 1 CxOUT 0 1 1 0
Input Conditions VIN- > VIN+ VIN- < VIN+ VIN- > VIN+ VIN- < VIN+ Note:
CxOUT refers to both the register bit and output pin.
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7.5 Comparator Response Time 7.6 Comparator Interrupt Operation
The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Specifications in Section 15.0 "Electrical Specifications" for more details. The comparator interrupt flag is set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive-or gate (see Figures 7-8 and 7-9). One latch is updated with the comparator output level when the CMCON0 register is read. This latch retains the value until the next read of the CMCON0 register or the occurrence of a Reset. The other latch of the mismatch circuit is updated on every Q1 system clock. A mismatch condition will occur when a comparator output change is clocked through the second latch on the Q1 clock cycle. The mismatch condition will persist, holding the CxIF bit of the PIR1 register true, until either the CMCON0 register is read or the comparator output returns to the previous state. Note: A write operation to the CMCON0 register will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle.
Software will need to maintain information about the status of the comparator output to determine the actual change that has occurred. The CxIF bit of the PIR1 register, is the comparator interrupt flag. This bit must be reset in software by clearing it to `0'. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. The CxIE bit of the PIE1 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CxIF bit of the PIR1 register will still be set if an interrupt condition occurs. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON0. This will end the mismatch condition. See Figures 7-8 and 7-9. Clear the CxIF interrupt flag.
A persistent mismatch condition will preclude clearing the CxIF interrupt flag. Reading CMCON0 will end the mismatch condition and allow the CxIF bit to be cleared. Note: If a change in the CMCON0 register (CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF interrupt flag may not get set.
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FIGURE 7-8: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ
Q1 Q3 CIN+ CxOUT Set CxIF (level) CxIF reset by software TRT
FIGURE 7-9:
COMPARATOR INTERRUPT TIMING WITH CMCON0 READ
Q1 Q3 CIN+ CxOUT Set CxIF (level) CxIF cleared by CMCON0 read reset by software TRT
Note 1: If a change in the CMCON0 register (CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF of the PIR1 register interrupt flag may not get set. 2: When either comparator is first enabled, bias circuitry in the Comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts.
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7.7 Operation During Sleep 7.8 Effects of a Reset
The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 15.0 "Electrical Specifications". If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. The comparator is turned off by selecting mode CM<2:0> = 000 or CM<2:0> = 111 of the CMCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CxIE bit of the PIE1 register and the PEIE bit of the INTCON register must be set. The instruction following the Sleep instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. A device Reset forces the CMCON0 and CMCON1 registers to their Reset states. This forces the Comparator module to be in the Comparator Reset mode (CM<2:0> = 000). Thus, all comparator inputs are analog inputs with the comparator disabled to consume the smallest current possible.
REGISTER 7-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
CMCON0: COMPARATOR CONFIGURATION REGISTER (PIC12F635)
R-0 COUT U-0 -- R/W-0 CINV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0
W = Writable bit `1' = Bit is set Unimplemented: Read as `0' COUT: Comparator Output bit When CINV = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CINV = 1: 1 = VIN+ < VIN0 = VIN+ > VINUnimplemented: Read as `0' CINV: Comparator Output Inversion bit 1 = Output inverted 0 = Output not inverted CIS: Comparator Input Switch bit When CM<2:0> = 110 or 101: 1 = CIN+ connects to VIN0 = CIN- connects to VINWhen CM<2:0> = 0xx or 100 or 111: CIS has no effect.
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 5 bit 4
bit 3
bit 2-0
CM<2:0>: Comparator Mode bits (See Figure 7-5) 000 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output turned off 001 = CIN pins are configured as analog, COUT pin configured as Comparator output 010 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output available internally 011 = CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin configured as Comparator output, CVREF is non-inverting input 100 = CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin is configured as I/O, Comparator output available internally, CVREF is non-inverting input 101 = CIN pins are configured as analog and multiplexed, COUT pin is configured as Comparator output, CVREF is non-inverting input 110 = CIN pins are configured as analog and multiplexed, COUT pin is configured as I/O, Comparator output available internally, CVREF is non-inverting input 111 = CIN pins are configured as I/O, COUT pin is configured as I/O, Comparator output disabled, Comparator off.
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PIC12F635/PIC16F636/639
REGISTER 7-2:
R-0 C2OUT bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CMCON0: COMPARATOR CONFIGURATION REGISTER (PIC16F636/639)
R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0
C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VINC1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VINC2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 Output inverted 0 = C1 Output not inverted CIS: Comparator Input Switch bit When CM<2:0> = 010: 1 = C1IN+ connects to C1 VINC2IN+ connects to C2 VIN0 = C1IN- connects to C1 VINC2IN- connects to C2 VINWhen CM<2:0> = 001: 1 = C1IN+ connects to C1 VIN0 = C1IN- connects to C1 VINCM<2:0>: Comparator Mode bits (See Figure 7-5) 000 = Comparators off. CxIN pins are configured as analog 001 = Three inputs multiplexed to two comparators 010 = Four inputs multiplexed to two comparators 011 = Two common reference comparators 100 = Two independent comparators 101 = One independent comparator 110 = Two comparators with outputs and common reference 111 = Comparators off. CxIN pins are configured as digital I/O
bit 6
bit 5
bit 4
bit 3
bit 2-0
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7.9 Comparator Gating Timer1
This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of the comparator (or Comparator C2 for PIC16F636/639). This requires that Timer1 is on and gating is enabled. See Section 6.0 "Timer1 Module with Gate Control" for details. It is recommended to synchronize the comparator with Timer1 by setting the CxSYNC bit when the comparator is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment. Note: References to the comparator in this section specifically are referring to Comparator C2 on the PIC16F636/639.
7.10
Synchronizing Comparator Output to Timer1
The comparator (or Comparator C2 for PIC16F636/639) output can be synchronized with Timer1 by setting the CxSYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 7-2) and the Timer1 Block Diagram (Figure 6-1) for more information. Note: References to the comparator in this section specifically are referring to Comparator C2 on the PIC16F636/639.
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PIC12F635/PIC16F636/639
REGISTER 7-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CMCON1: COMPARATOR CONFIGURATION REGISTER (PIC12F635)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 T1GSS R/W-0 CMSYNC bit 0
Unimplemented: Read as `0' T1GSS: Timer1 Gate Source Select bit(1) 1 = Timer1 Gate Source is T1G pin (pin should be configured as digital input) 0 = Timer1 Gate Source is comparator output CMSYNC: Comparator Output Synchronization bit(2) 1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Refer to Section 6.6 "Timer1 Gate". Refer to Figure 7-2.
bit 0
Note 1: 2:
REGISTER 7-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1
CMCON1: COMPARATOR CONFIGURATION REGISTER (PIC16F636/639)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 T1GSS R/W-0 C2SYNC bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' T1GSS: Timer1 Gate Source Select bit(1) 1 = Timer1 gate source is T1G pin (pin should be configured as digital input) 0 = Timer1 gate source is Comparator C2 output C2SYNC: Comparator C2 Output Synchronization bit(2) 1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Refer to Section 6.6 "Timer1 Gate". Refer to Figure 7-4.
bit 0
Note 1: 2:
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7.11 Comparator Voltage Reference
7.11.3 OUTPUT CLAMPED TO VSS
The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available: * * * * * Independent from Comparator operation Two 16-level voltage ranges Output clamped to VSS Ratiometric with VDD Fixed Voltage Reference The CVREF output voltage can be set to Vss with no power consumption by configuring VRCON as follows: * VREN = 0 * VRR = 1 * VR<3:0> = 0000 This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current.
The VRCON register (Register 7-5) controls the Voltage Reference module shown in Figure 7-10.
7.11.4
OUTPUT RATIOMETRIC TO VDD
7.11.1
INDEPENDENT OPERATION
The comparator voltage reference is independent of the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference.
The comparator voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 15.0 "Electrical Specifications".
7.11.2
OUTPUT VOLTAGE SELECTION
The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON register.
The CVREF output voltage is determined by the following
equations:
EQUATION 7-1:
CVREF OUTPUT VOLTAGE (INTERNAL CVREF)
VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR<3:0> x VDD/32)
EQUATION 7-2:
VRR = 1 (low range):
CVREF OUTPUT VOLTAGE (EXTERNAL CVREF)
CVREF = (VR<3:0>/24) x VLADDER VRR = 0 (high range): CVREF = (VLADDER/4) + (VR<3:0> x VLADDER/32) VLADDER = VDD or ([VREF+] - [VREF-]) or VREF+ The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure 7-10.
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REGISTER 7-5:
R/W-0 VREN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
U-0 -- R/W-0 VRR U-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0
VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS. Unimplemented: Read as `0' VRR: CVREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as `0' VR<3:0>: CVREF Value Selection bits (0 VR<3:0> 15) When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
bit 6 bit 5
bit 4 bit 3-0
FIGURE 7-10:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages 8R R R R R
VDD 8R 16-1 Analog MUX VREN CVREF to Comparator Input
15 14 2 1 0
VRR
VR<3:0>(1)
VREN VR<3:0> = 0000 VRR
Note 1:
Care should be taken to ensure VREF remains within the comparator common mode input range. See Section 15.0 "Electrical Specifications" for more detail.
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TABLE 7-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES
Bit 7 -- -- GIE EEIE EEIF -- -- -- -- VREN Bit 6 COUT -- PEIE LVDIE LVDIF -- -- -- -- -- Bit 5 -- -- T0IE CRIE CRIF RA5 RC5 Bit 4 CINV -- INTE -- -- RA4 RC4 Bit 3 CIS -- RAIE C1IE C1IF RA3 RC3 Bit 2 CM2 -- T0IF OSFIE OSFIF RA2 RC2 Bit 1 CM1 T1GSS INTF -- -- RA1 RC1 TRISA1 TRISC1 VR1 Bit 0 CM0 CMSYNC RAIF TMR1IE TMR1IF RA0 RC0 TRISA0 TRISC0 VR0 Value on POR, BOR -0-0 0000 ---- --10 0000 000x 000- 00-0 000- 00-0 --xx xxxx --xx xxxx --11 1111 --11 1111 0-0- 0000 Value on all other Resets -0-0 0000 ---- --10 0000 000x 000- 00-0 000- 00-0 --uu uuuu --uu uuuu --11 1111 --11 1111 0-0- 0000
Name CMCON0 CMCON1 INTCON PIE1 PIR1 PORTA PORTC TRISA TRISC VRCON Legend:
TRISA5 TRISA4 TRISA3 TRISA2 TRISC5 TRISC4 TRISC3 TRISC2 VRR -- VR3 VR2
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used for comparator.
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NOTES:
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8.0 PROGRAMMABLE LOW-VOLTAGE DETECT (PLVD) MODULE
The PLVD module includes the following capabilities: * * * * Eight programmable trip points Interrupt on falling VDD Stable reference indication Operation during Sleep
The Programmable Low-Voltage Detect (PLVD) module is a power supply detector which monitors the internal power supply. This module is typically used in key fobs and other devices, where certain actions need to be taken as a result of a falling battery voltage.
A Block diagram of the PLVD module is shown in Figure 8-1.
FIGURE 8-1:
PLVD BLOCK DIAGRAM
8 Stages
VDD
8-to-1 Analog MUX LVDEN 0 1 2 6 7 LVDL<2:0> Reference Voltage Generator
+ det LVDIF
FIGURE 8-2:
PLVD OPERATION
VDD PLVD Trip Point
LVDIF Set by Hardware Cleared by Software
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8.1 PLVD Operation 8.4 Stable Reference Indication
To setup the PLVD for operation, the following steps must be taken: * Enable the module by setting the LVDEN bit of the LVDCON register. * Configure the trip point by setting the LVDL<2:0> bits of the LVDCON register. * Wait for the reference voltage to become stable. Refer to Section 8.4 "Stable Reference Indication". * Clear the LVDIF bit of the PIRx register. The LVDIF bit will be set when VDD falls below the PLVD trip point. The LVDIF bit remains set until cleared by software. Refer to Figure 8-2. When the PLVD module is enabled, the reference voltage must be allowed to stabilize before the PLVD will provide a valid result. Refer to Electrical Section, PLVD Characteristics for the stabilization time. When the HFINTOSC is running, the IRVST bit of the LVDCON register indicates the stability of the voltage reference. The voltage reference is stable when the IRVST bit is set.
8.5
Operation During Sleep
8.2
Programmable Trip Point
The PLVD trip point is selectable from one of eight voltage levels. The LVDL bits of the LVDCON register select the trip point. Refer to Register 8-1 for the available PLVD trip points.
To wake from Sleep, set the LVDIE bit of the PIEx register and the PEIE bit of the INTCON register. When the LVDIE and PEIE bits are set, the device will wake from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine upon completion of the first instruction after waking from Sleep.
8.3
Interrupt on Falling VDD
When VDD falls below the PLVD trip point, the falling edge detector will set the LVDIF bit. See Figure 8-2. An interrupt will be generated if the following bits are also set: * GIE and PEIE bits of the INTCON register * LVDIE bit of the PIEx register The LVDIF bit must be cleared by software. An interrupt can be generated from a simulated PLVD event when the LVDIF bit is set by software.
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PIC12F635/PIC16F636/639
REGISTER 8-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER
U-0 -- R-0 IRVST(1) R/W-0 LVDEN U-0 -- R/W-1 LVDL2 R/W-0 LVDL1 R/W-0 LVDL0 bit 0
Unimplemented: Read as `0' IRVST: Internal Reference Voltage Stable Status Flag bit(1) 1 = Indicates that the PLVD is stable and PLVD interrupt is reliable 0 = Indicates that the PLVD is not stable and PLVD interrupt must not be enabled LVDEN: Low-Voltage Detect Module Enable bit 1 = Enables PLVD Module, powers up PLVD circuit and supporting reference circuitry 0 = Disables PLVD Module, powers down PLVD circuit and supporting reference circuitry Unimplemented: Read as `0' LVDL<2:0>: Low-Voltage Detection Level bits (nominal values) 111 = 4.5V 110 = 4.2V 101 = 4.0V 100 = 2.3V (default) 011 = 2.2V 010 = 2.1V 001 = 2.0V(2) 000 = Reserved The IRVST bit is usable only when the HFINTOSC is running. Not tested and below minimum operating conditions.
bit 4
bit 3 bit 2-0
Note 1: 2:
TABLE 8-1:
Name INTCON PIE1 PIR1 LVDCON Legend:
REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT
Bit 7 GIE Bit 6 PEIE C2IE C2IF -- Bit 5 T0IE C1IE C1IF IRVST Bit 4 INTE LCDIE LCDIF LVDEN Bit 3 RAIE -- -- -- Bit 2 T0IF LVDIE LVDIF LVDL2 Bit 1 INTF -- -- LVDL1 Bit 0 RAIF CCP2IE CCP2IF LVDL0 Value on POR, BOR 0000 000x 0000 -0-0 0000 -0-0 --00 -100 Value on all other Resets 0000 000x 0000 -0-0 0000 -0-0 --00 -100
OSFIE OSFIF --
x = unknown, - = unimplemented read as `0'. Shaded cells are not used by the PLVD module.
(c) 2007 Microchip Technology Inc.
DS41232D-page 89
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NOTES:
DS41232D-page 90
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
9.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory: * * * * EECON1 EECON2 (not a physically implemented register) EEDAT EEADR The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as from chip-to-chip. Please refer to A/C specifications in Section 15.0 "Electrical Specifications" for exact limits. When the data memory is code-protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access the data EEPROM data and will read zeroes.
EEDAT holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. PIC16F636/639 has 256 bytes of data EEPROM and the PIC12F635 has 128 bytes.
REGISTER 9-1:
R/W-0 EEDAT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
EEDAT: EEPROM DATA REGISTER
R/W-0 EEDAT6 R/W-0 EEDAT5 R/W-0 EEDAT4 R/W-0 EEDAT3 R/W-0 EEDAT2 R/W-0 EEDAT1 R/W-0 EEDAT0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEDATn: Byte Value to Write To or Read From Data EEPROM bits
REGISTER 9-2:
R/W-0 EEADR7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 Note 1:
(1)
EEADR: EEPROM ADDRESS REGISTER
R/W-0 EEADR6 R/W-0 EEADR5 R/W-0 EEADR4 R/W-0 EEADR3 R/W-0 EEADR2 R/W-0 EEADR1 R/W-0 EEADR0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEADR: Specifies One of 256 Locations for EEPROM Read/Write Operation bits PIC16F636/639 only. Read as `0' on PIC12F635.
(c) 2007 Microchip Technology Inc.
DS41232D-page 91
PIC12F635/PIC16F636/639
9.1 EECON1 AND EECON2 Registers
EECON1 is the control register with four low-order bits physically implemented. The upper four bits are non-implemented and read as `0's. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit, clear it and rewrite the location. The data and address will be cleared. Therefore, the EEDAT and EEADR registers will need to be re-initialized. Interrupt flag, EEIF bit of the PIR1 register, is set when write is complete. This bit must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the data EEPROM write sequence. Note: The EECON1, EEDAT and EEADR registers should not be modified during a data EEPROM write (WR bit = 1).
REGISTER 9-3:
U-0 -- bit 7 Legend:
EECON1: EEPROM CONTROL REGISTER
U-0 -- U-0 -- U-0 -- R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
S = Bit can only be set R = Readable bit -n = Value at POR bit 7-4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOR Reset) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set, not cleared, in software.) 0 = Does not initiate an EEPROM read
bit 2
bit 1
bit 0
DS41232D-page 92
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
9.2 Reading the EEPROM Data Memory 9.4 Write Verify
Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 9-3) to the desired value to be written.
To read a data memory location, the user must write the address to the EEADR register and then set control bit RD of the EECON1 register, as shown in Example 9-1. The data is available, in the very next cycle, in the EEDAT register. Therefore, it can be read in the next instruction. EEDAT holds this value until another read, or until it is written to by the user (during a write operation).
EXAMPLE 9-3:
BANKSEL MOVF BSF XORWF BTFSS GOTO :
WRITE VERIFY
EXAMPLE 9-1:
BANKSEL MOVLW MOVWF BSF MOVF
DATA EEPROM READ
; ; ;Address to read ;EE Read ;Move data to W
EEADR CONFIG_ADDR EEADR EECON1,RD EEDAT,W
; ;EEDAT not changed ;from previous write EECON1,RD ;YES, Read the ;value written EEDAT,W ; STATUS,Z ;Is data the same WRITE_ERR ;No, handle error ;Yes, continue
EEDAT EEDAT,W
9.3
Writing to the EEPROM Data Memory
9.4.1
USING THE DATA EEPROM
To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDAT register. Then the user must follow a specific sequence to initiate the write for each byte, as shown in Example 9-2. The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. A cycle count is executed during the required sequence. Any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the EEPROM. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. The EEIF bit of the PIR1 register must be cleared by software.
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM (specification D124) without exceeding the total number of write cycles to a single byte (specifications D120 and D120A). If this is the case, then a refresh of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory.
EXAMPLE 9-2:
BANKSEL BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF
DATA EEPROM WRITE
; ;Enable write ;Disable INTs ;Unlock write ; ; ; ;Start the write ;Enable INTS
EEADR EECON1,WREN INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE
(c) 2007 Microchip Technology Inc.
Required Sequence
DS41232D-page 93
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9.5 Protection Against Spurious Write 9.6
There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (nominal 64 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: * Brown-out * Power Glitch * Software Malfunction
Data EEPROM Operation During Code Protection
Data memory can be code-protected by programming the CPD bit in the Configuration Word (Register 12-1) to `0'. When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations in program memory to `0' will also help prevent data memory code protection from becoming breached.
TABLE 9-1:
Name INTCON PIR1 PIE1 EEDAT EEADR EECON1 EECON2
SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
Bit 7 GIE EEIF EEIE Bit 6 PEIE LVDIF LVDIE EEDAT6 EEADR6 -- Bit 5 T0IE CRIF CRIE EEDAT5 EEADR5 -- Bit 4 INTE C2IF(1) C2IE(1) EEDAT4 EEADR4 -- Bit 3 RAIE C1IF C1IE EEDAT3 EEADR3 WRERR Bit 2 T0IF OSFIF OSFIE EEDAT2 EEADR2 WREN Bit 1 INTF -- -- EEDAT1 EEADR1 WR Bit 0 RAIF TMR1IF TMR1IE EEDAT0 EEADR0 RD Value on POR, BOR 0000 000x 0000 00-0 0000 00-0 0000 0000 0000 0000 ---- x000 ---- ---Value on all other Resets 0000 000x 0000 00-0 0000 00-0 0000 0000 0000 0000 ---- q000 ---- ----
EEDAT7 EEADR7(1) --
EEPROM Control Register 2 (not a physical register)
Legend: Note 1:
x = unknown, u = unchanged, - = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by the data EEPROM module. PIC16F636/639 only.
DS41232D-page 94
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
10.0 KEELOQ(R) COMPATIBLE CRYPTOGRAPHIC MODULE
To obtain information regarding the implementation of the KEELOQ module, Microchip Technology requires the execution of the "KEELOQ(R) Encoder License Agreement". The "KEELOQ(R) Encoder License Agreement" may be accessed through the Microchip web site located at www.microchip.com/KEELOQ. Further information may be obtained by contacting your local Microchip Sales Representative.
(c) 2007 Microchip Technology Inc.
DS41232D-page 95
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NOTES:
DS41232D-page 96
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
11.0 ANALOG FRONT-END (AFE) FUNCTIONAL DESCRIPTION (PIC16F639 ONLY)
11.2 Modulation Circuit
The modulation circuit consists of a modulation transistor (FET), internal tuning capacitors and external LC antenna components. The modulation transistor and the internal tuning capacitors are connected between the LC input pin and LCCOM pin. Each LC input has its own modulation transistor. When the modulation transistor turns on, its low Turn-on Resistance (RM) clamps the induced LC antenna voltage. The coil voltage is minimized when the modulation transistor turns-on and maximized when the modulation transistor turns-off. The modulation transistor's low Turn-on Resistance (RM) results in a high modulation depth. The LF talk-back is achieved by turning on and off the modulation transistor. The modulation data comes from the microcontroller section via the digital SPI interface as "Clamp On", "Clamp Off" commands. Only those inputs that are enabled will execute the clamp command. A basic block diagram of the modulation circuit is shown in Figure 11-1 and Figure 11-2. The modulation FET is also shorted momentarily after Soft Reset and Inactivity timer time-out.
The PIC16F639 device consists of the PIC16F636 device and low frequency (LF) Analog Front-End (AFE), with the AFE section containing three analog-input channels for signal detection and LF talk-back. This section describes the Analog Front-End (AFE) in detail. The PIC16F639 device can detect a 125 kHz input signal as low as 1 mVpp and transmit data by using internal LF talk-back modulation or via an external transmitter. The PIC16F639 can also be used for various bidirectional communication applications. Figure 11-3 and Figure 11-4 show application examples of the device. Each analog input channel has internal tuning capacitance, sensitivity control circuits, an input signal strength limiter and an LF talk-back modulation transistor. An Automatic Gain Control (AGC) loop is used for all three input channel gains. The output of each channel is OR'd and fed into a demodulator. The digital output is passed to the LFDATA pin. Figure 11-1 shows the block diagram of the AFE and Figure 11-2 shows the LC input path. There are a total of eight Configuration registers. Six of them are used for AFE operation options, one for column parity bits and one for status indication of AFE operation. Each register has 9 bits including one row parity bit. These registers are readable and writable by SPI (Serial Protocol Interface) commands except for the STATUS register, which is read-only.
11.3
Tuning Capacitor
Each channel has internal tuning capacitors for external antenna tuning. The capacitor values are programmed by the Configuration registers up to 63 pF, 1 pF per step. Note: The user can control the tuning capacitor by programming the AFE Configuration registers.
11.1
RF Limiter 11.4 Variable Attenuator
The variable attenuator is used to attenuate, via AGC control, the input signal voltage to avoid saturating the amplifiers and demodulators. Note: The variable attenuator function is accomplished by the device itself. The user cannot control its function.
The RF Limiter limits LC pin input voltage by de-Q'ing the attached LC resonant circuit. The absolute voltage limit is defined by the silicon process's maximum allowed input voltage (see Section 15.0 "Electrical Specifications"). The limiter begins de-Q'ing the external LC antenna when the input voltage exceeds VDE_Q, progressively de-Q'ing harder to reduce the antenna input voltage. The signal levels from all 3 channels are combined such that the limiter attenuates all 3 channels uniformly, in respect to the channel with the strongest signal.
11.5
Sensitivity Control
The sensitivity of each channel can be reduced by the channel's Configuration register sensitivity setting. This is used to desensitize the channel from optimum. Note: The user can desensitize the channel sensitivity by programming the AFE Configuration registers.
(c) 2007 Microchip Technology Inc.
DS41232D-page 97
PIC12F635/PIC16F636/639
11.6 AGC Control 11.10 Demodulator
The Demodulator consists of a full-wave rectifier, low pass filter, peak detector and Data Slicer that detects the envelope of the input signal. The AGC controls the variable attenuator to limit the internal signal voltage to avoid saturation of internal amplifiers and demodulators (Refer to Section 11.4 "Variable Attenuator"). The signal levels from all 3 channels are combined such that AGC attenuates all 3 channels uniformly in respect to the channel with the strongest signal. Note: The AGC control function is accomplished by the device itself. The user cannot control its function.
11.11 Data Slicer
The Data Slicer consists of a reference generator and comparator. The Data Slicer compares the input with the reference voltage. The reference voltage comes from the minimum modulation depth requirement setting and input peak voltage. The data from all 3 channels are OR'd together and sent to the output enable filter.
11.7
Fixed Gain Amplifiers 1 and 2
FGA1 and FGA2 provides a maximum two-stage gain of 40 dB. Note: The user cannot control the gain of these two amplifiers.
11.12 Output Enable Filter
The Output Enable Filter enables the LFDATA output once the incoming signal meets the wake-up sequence requirements (see Section 11.15 "Configurable Output Enable Filter").
11.8
Auto Channel Selection 11.13 RSSI (Received Signal Strength Indicator)
The RSSI provides a current which is proportional to the input signal amplitude (see Section 11.31.3 "Received Signal Strength Indicator (RSSI) Output").
The Auto Channel Selection feature is enabled if the Auto Channel Select bit AUTOCHSEL<8> in Configuration Register 5 (Register 11-6) is set, and disabled if the bit is cleared. When this feature is active (i.e., AUTOCHSE <8> = 1), the control circuit checks the demodulator output of each input channel immediately after the AGC settling time (TSTAB). If the output is high, it allows this channel to pass data, otherwise it is blocked. The status of this operation is monitored by AFE Status Register 7 bits <8:6> (Register 11-8). These bits indicate the current status of the channel selection activity, and automatically updates for every Soft Reset period. The auto channel selection function resets after each Soft Reset (or after Inactivity timer time-out). Therefore, the blocked channels are reenabled after Soft Reset. This feature can make the output signal cleaner by blocking any channel that was not high at the end of TAGC. This function works only for demodulated data output, and is not applied for carrier clock or RSSI output.
11.14 Analog Front-End Timers
The AFE has an internal 32 kHz RC oscillator. The oscillator is used in several timers: * Inactivity timer * Alarm timer * Pulse Width timer * Period timer * AGC settling timer
11.14.1
RC OSCILLATOR
The RC oscillator is low power, 32 kHz 10% over temperature and voltage variations.
11.9
Carrier Clock Detector
The Detector senses the input carrier cycles. The output of the Detector switches digitally at the signal carrier frequency. Carrier clock output is available when the output is selected by the DATOUT bit in the AFE Configuration Register 1 (Register 11-2).
DS41232D-page 98
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
11.14.2 INACTIVITY TIMER
The timer is reset when the: * CS pin is low (any SPI command). * Output enable filter is disabled. * LFDATA pin is enabled (signal passed output enable filter). The timer starts when: * Receiving a LF signal. The timer causes a low output on the ALERT pin when: * Output enable filter is enabled and modulated input signal is present for TALARM, but does not pass the output enable filter requirement. Note: The Alarm timer is disabled if the output enable filter is disabled. The Inactivity Timer is used to automatically return the AFE to Standby mode, if there is no input signal. The time-out period is approximately 16 ms (TINACT), based on the 32 kHz internal clock. The purpose of the Inactivity Timer is to minimize AFE current draw by automatically returning the AFE to the lower current Standby mode, if there is no input signal for approximately 16 ms. The timer is reset when: * An amplitude change in LF input signal, either high-to-low or low-to-high * CS pin is low (any SPI command) * Timer-related Soft Reset The timer starts when: * AFE receives any LF signal The timer causes an AFE Soft Reset when: * A previously received LF signal does not change either high-to-low or low-to-high for TINACT The Soft Reset returns the AFE to Standby mode where most of the analog circuits, such as the AGC, demodulator and RC oscillator, are powered down. This returns the AFE to the lower Standby Current mode.
11.14.4
PULSE WIDTH TIMER
The Pulse Width Timer is used to verify that the received output enable sequence meets both the minimum TOEH and minimum TOEL requirements.
11.14.5
PERIOD TIMER
The Period Timer is used to verify that the received output enable sequence meets the maximum TOET requirement.
11.14.3
ALARM TIMER
11.14.6
AGC SETTLING TIMER (TAGC)
The Alarm Timer is used to notify the MCU that the AFE is receiving LF signal that does not pass the output enable filter requirement. The time-out period is approximately 32 ms (TALARM) in the presence of continuing noise. The Alarm Timer time-out occurs if there is an input signal for longer than 32 ms that does not meet the output enable filter requirements. The Alarm Timer time-out causes: a) b) The ALERT pin to go low. The ALARM bit to set in the AFE Status Configuration 7 register (Register 11-8).
This timer is used to keep the output enable filter in Reset while the AGC settles on the input signal. The time-out period is approximately 3.5 ms. At end of this time (TAGC), the input should remain high (TPAGC), otherwise the counting is aborted and a Soft Reset is issued. See Figure 11-6 for details. Note 1: The AFE needs continuous and uninterrupted high input signal during AGC settling time (TAGC). Any absence of signal during this time may reset the timer and a new input signal is needed for AGC settling time, or may result in improper AGC gain settings which will produce invalid output. 2: The rest of the AFE section wakes up if any of these input channels receive the AGC settling time correctly. AFE Status Register 7 bits <4:2> (Register 11-8) indicate which input channels have waken up the AFE first. Valid input signal on multiple input pins can cause more than one channel's indicator bit to be set.
The MCU is informed of the Alarm timer time-out by monitoring the ALERT pin. If the Alarm timer time-out occurs, the MCU can take appropriate actions such as lowering channel sensitivity or disabling channels. If the noise source is ignored, the AFE can return to a lower standby current draw state.
(c) 2007 Microchip Technology Inc.
DS41232D-page 99
PIC12F635/PIC16F636/639
FIGURE 11-1: FUNCTIONAL BLOCK DIAGRAM - ANALOG FRONT-END
LCX
AGC Detector RF Lim Tune X Mod Sensitivity Control X
/ 64 WAKEX
A
/ 64 LCCOM WAKEY LCY AGC Detector RF Lim Tune Y Mod Sensitivity Control Y A WAKEZ
LCCOM / 64 Detector RF Lim Tune Z Mod Sensitivity Control Z Watchdog A
LCZ
AGC
Modulation Depth LCCOM To Sensitivity X To Sensitivity Y To Sensitivity Z AGC Preserve To Modulation Transistors To Tuning Cap X To Tuning Cap Y To Tuning Cap Z 32 kHZ Oscillator AGC Timer
B
Output Enable Filter
Command Decoder/Controller
Configuration Registers
VSST
VDDT
RSSI
SCLK/ALERT
CS
LFDATA/RSSI/ CCLK/SDIO
MCU
DS41232D-page 100
(c) 2007 Microchip Technology Inc.
FIGURE 11-2:
AGC
FGA1 Var Atten Carrier Detector LFDATA Output Enable Filter / 64 - /1 OR /4 DETX DETY DETZ C A CLKDIV RSSI GEN 00 01 10 11 +
LCX/ LCY/ LCZ
FGA2
RF Limiter
MOD FET
Capacitor Tuning
Sens. Control
(c) 2007 Microchip Technology Inc.
> 4 VPP
LC INPUT PATH
LFDATA DATOUT
WAKEX WAKEY WAKEZ 32 kHz Clock/AGC Timer
LCCOM
RSSI 1 0 AGCSIG
C
0.1V
-
Configuration
0.4V
Decode
Registers Full-Wave Rectifier X Y Z Low-Pass Filter Peak Detector AGC Feedback Amplifier + AGCACT
A
Legend:
Demodulator
REF GEN
MOD Depth Control Data Slicer - + AUTOCHSEL Auto Channel Selector X Y Z B CHX CHY CHZ ACT
FGA = Fixed Gain Amplifier
FWR = Full-wave Rectifier
LPF = Low-pass Filter
PIC12F635/PIC16F636/639
DS41232D-page 101
PD = Peak Detector
PIC12F635/PIC16F636/639
FIGURE 11-3:
BIDIRECTIONAL PASSIVE KEYLESS ENTRY (PKE) SYSTEM APPLICATION EXAMPLE
d Encrypte des Co se Respon HF) (U
LED
LED
UHF Receiver Microcontroller (MCU)
mand LF Com z) 25 kH (1
UHF Transmitter Ant. X PIC16F639 Ant. Y MCU (PIC16F636) + Ant. Z 3 Input Analog Front-End
LF Transmitter/ Receiver
LF Talk-Back (125 kHz)
Base Station
Transponder
FIGURE 11-4:
PASSIVE KEYLESS ENTRY (PKE) TRANSPONDER CONFIGURATION EXAMPLE
315 MHz
+3V VDD S0 S1 S2 1 2 3 4 20 19 18 S5 17 VSS +3V S3 S4 +3V
PIC16F639
RF Circuitry (UHF TX)
Data RFEN LFDATA/RSSI/CCLK/SDIO
5 6 7 8 9 10
16 15 14 13 12 11
LED CS SCLK/ALERT VSST LCCOM LCZ
+3V VDDT LCX LCY air-core coil
ferrite-core coil
ferrite-core coil
DS41232D-page 102
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
11.15 Configurable Output Enable Filter
The purpose of this filter is to enable the LFDATA output and wake the microcontroller only after receiving a specific sequence of pulses on the LC input pins. Therefore, it prevents the AFE from waking up the microcontroller due to noise or unwanted input signals. The circuit compares the timing of the demodulated header waveform with a pre-defined value, and enables the demodulated LFDATA output when a match occurs. The output enable filter consists of a high (TOEH) and low duration (TOEL) of a pulse immediately after the AGC settling gap time. The selection of high and low times further implies a max period time. The output enable high and low times are determined by SPI interface programming. Figure 11-5 and Figure 11-6 show the output enable filter waveforms. There should be no missing cycles during TOEH. Missing cycles may result in failing the output enable condition.
FIGURE 11-5:
OUTPUT ENABLE FILTER TIMING
Required Output Enable Sequence TSTAB (TAGC + TPAGC) Data Packet TGAP t TOEH t TOEL Start bit LFDATA output is enabled on this rising edge
Demodulator Output
AFE Wake-up
and AGC Stabilization
AGC Gap Pulse
t TOET
(c) 2007 Microchip Technology Inc.
DS41232D-page 103
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FIGURE 11-6: OUTPUT ENABLE FILTER TIMING EXAMPLE (DETAILED)
LFDATA Output
Start bit
3.5 ms
LF Coil Input
Low Current Standby Mode
TAGC (AGC settling time)
TPAGC TGAP (need Gap "high") Pulse
t TOEL t TOEH t TOET
t TE
TSTAB (AFE Stabilization)
Filter starts
Filter is passed and LFDATA is enabled
Legend:
TAGC = AGC stabilization time TE = Time element of pulse TGAP = AGC stabilization gap TOEH = Minimum output enable filter high time TOEL = Minimum output enable filter low time TOET = Maximum output enable filter period TPAGC = High time after TAGC TSTAB = TAGC + TPAGC
DS41232D-page 104
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 11-1:
OEH <1:0> 01 01 01 01 10 10 10 10 11 11 11 11 00 Note 1:
TYPICAL OUTPUT ENABLE FILTER TIMING
TOEH (ms) 1 1 1 1 2 2 2 2 4 4 4 4 TOEL (ms) 1 1 2 4 1 1 2 4 1 1 2 4 Filter Disabled TOET (ms) 3 3 4 6 4 4 5 8 6 6 8 10
OEL <1:0> 00 01 10 11 00 01 10 11 00 01 10 11
XX
If the filter resets due to a long high (TOEH > TOET), the high-pulse timer will not begin timing again until after a gap of TE and another low-to-high transition occurs on the demodulator output. Disabling the output enable filter disables the TOEH and TOEL requirement and the AFE passes all received LF data. See Figure 11-10, Figure 11-11 and Figure 11-12 for examples. When viewed from an application perspective, from the pin input, the actual output enable filter timing must factor in the analog delays in the input path (such as demodulator charge and discharge times). * TOEH - TDR + TDF * TOEL + TDR - TDF The output enable filter starts immediately after TGAP, the gap after AGC stabilization period.
11.16 Input Sensitivity Control
The AFE is designed to have typical input sensitivity of 3 mVPP. This means any input signal with amplitude greater than 3 mVPP can be detected. The AFE's internal AGC loop regulates the detecting signal amplitude when the input level is greater than approximately 20 mVPP. This signal amplitude is called "AGC-active level". The AGC loop regulates the input voltage so that the input signal amplitude range will be kept within the linear range of the detection circuits without saturation. The AGC Active Status bit AGCACT<5>, in the AFE Status Register 7 (Register 11-8) is set if the AGC loop regulates the input voltage. Table 11-2 shows the input sensitivity comparison when the AGCSIG option is used. When AGCSIG option bit is set, the demodulated output is available only when the AGC loop is active (see Table 11-1). The AFE has also input sensitivity reduction options per each channel. The Configuration Register 3 (Register 11-4), Configuration Register 4 (Register 11-5) and Configuration Register 5 (Register 11-6) have the option to reduce the channel gains from 0 dB to approximately -30 dB.
Typical at room temperature and VDD = 3.0V, 32 kHz oscillator.
TOEH is measured from the rising edge of the demodulator output to the first falling edge. The pulse width must fall within TOEH t TOET. TOEL is measured from the falling edge of the demodulator output to the rising edge of the next pulse. The pulse width must fall within TOEL t TOET. TOET is measured from rising edge to the next rising edge (i.e., the sum of TOEH and TOEL). The pulse width must be t TOET. If the Configuration Register 0 (Register 11-1), OEL<8:7> is set to `00', then TOEH must not exceed TOET and TOEL must not exceed TINACT. The filter will reset, requiring a complete new successive high and low period to enable LFDATA, under the following conditions. * The received high is not greater than the configured minimum TOEH value. * During TOEH, a loss of signal > 56 s. A loss of signal < 56 s may or may not cause a filter Reset. * The received low is not greater than the configured minimum TOEL value. * The received sequence exceeds the maximum TOET value: - TOEH + TOEL > TOET - or TOEH > TOET - or TOEL > TOET * A Soft Reset SPI command is received.
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TABLE 11-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>)
Description Disabled - the AFE passes signal of any amplitude level it is capable of detecting (demodulated data and carrier clock). Enabled - No output until AGC Status = 1 (i.e., VPEAK 20 mVPP) (demodulated data and carrier clock). * Provides the best signal to noise ratio. Input Sensitivity (Typical) 3.0 mVPP 20 mVPP AGCSIG<7> (Config. Register 5) 0 1
11.17 Input Channels (Enable/Disable)
Each channel can be individually enabled or disabled by programming bits in Configuration Register 0<3:1> (Register 11-1). The purpose of having an option to disable a particular channel is to minimize current draw by powering down as much circuitry as possible, if the channel is not needed for operation. The exact circuits disabled when an input is disabled are amplifiers, detector, full-wave rectifier, data slicer, and modulation FET. However, the RF input limiter remains active to protect the silicon from excessive antenna input voltages.
11.19 AGC Preserve
The AGC preserve feature allows the AFE to preserve the AGC value during the AGC settling time (TAGC) and apply the value to the data slicing circuit for the following data streams instead of using a new tracking value. This feature is useful to demodulate the input signal correctly when the input has random amplitude variations at a given time period. This feature is enabled when the AFE receives an AGC Preserve On command and disabled if it receives an AGC Preserve Off command. Once the AGC Preserve On command is received, the AFE acquires a new AGC value during each AGC settling time and preserves the value until a Soft Reset or an AGC Preserve Off command is issued. Therefore, it does not need to issue another AGC Preserve On command. An AGC Preserve Off command is needed to disable the AGC preserve feature (see Section 11.32.2.5 "AGC Preserve On Command" and Section 11.32.2.6 "AGC Preserve Off Command" for AGC Preserve commands).
11.18 AGC Amplifier
The circuit automatically amplifies input signal voltage levels to an acceptable level for the data slicer. Fast attack and slow release by nature, the AGC tracks the carrier signal level and not the modulated data bits. The AGC inherently tracks the strongest of the three antenna input signals. The AGC requires an AGC stabilization time (TAGC). The AGC will attempt to regulate a channel's peak signal voltage into the data slicer to a desired regulated AGC voltage - reducing the input path's gain as the signal level attempts to increase above regulated AGC voltage, and allowing full amplification on signal levels below the regulated AGC voltage. The AGC has two modes of operation: 1. During the AGC settling time (TAGC), the AGC time constant is fast, allowing a reasonably short acquisition time of the continuous input signal. After TAGC, the AGC switches to a slower time constant for data slicing.
2.
Also, the AGC is frozen when the input signal envelope is low. The AGC tracks only high envelope levels.
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11.20 Soft Reset
The AFE issues a Soft Reset in the following events: a) b) c) d) After Power-on Reset (POR), After Inactivity timer time-out, If an "Abort" occurs, After receiving SPI Soft Reset command.
TABLE 11-3:
SETTING FOR MINIMUM MODULATION DEPTH REQUIREMENT
Modulation Depth
MODMIN Bits (Config. Register 5) Bit 6 0 0 1 1 Bit 5 0 1 0 1
The "Abort" occurs if there is no positive signal detected at the end of the AGC stabilization period (TAGC). The Soft Reset initializes internal circuits and brings the AFE into a low current Standby mode operation. The internal circuits that are initialized by the Soft Reset include: * * * * Output Enable Filter AGC circuits Demodulator 32 kHz Internal Oscillator
50% (default) 75% 25% 12%
The Soft Reset has no effect on the Configuration register setup, except for some of the AFE Status Register 7 bits. (Register 11-8). The circuit initialization takes one internal clock cycle (1/32 kHz = 31.25 s). During the initialization, the modulation transistors between each input and LCCOM pins are turned-on to discharge any internal/external parasitic charges. The modulation transistors are turned-off immediately after the initialization time. The Soft Reset is executed in Active mode only. It is not valid in Standby mode.
11.21 Minimum Modulation Depth Requirement for Input Signal
The AFE demodulates the modulated input signal if the modulation depth of the input signal is greater than the minimum requirement that is programmed in the AFE Configuration Register 5 (Register 11-6). Figure 11-7 shows the definition of the modulation depth and examples. MODMIN<6:5> of the Configuration Register 5 offer four options. They are 75%, 50%, 25% and 12%, with a default setting of 50%. The purpose of this feature is to enhance the demodulation integrity of the input signal. The 12% setting is the best choice for the input signal with weak modulation depth, which is typically observed near the high-voltage base station antenna and also at far-distance from the base station antenna. It gives the best demodulation sensitivity, but is very susceptible to noise spikes that can result in a bit detection error. The 75% setting can reduce the bit errors caused by noise, but gives the least demodulation sensitivity. See Table 11-3 for minimum modulation depth requirement settings.
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FIGURE 11-7:
MODULATION DEPTH EXAMPLES (a) Modulation Depth Definition Amplitude Modulation Depth (%) = t B A A-B A X 100%
(b) LFDATA Output vs. Input vs. Minimum Modulation Depth Setting Amplitude 7 mVPP 10 mVPP Coil Input Strength Modulation Depth (%) = t 10 - 7 X 100% = 30% 10
Input signal with modulation depth = 30%
Demodulated LFDATA Output when MODMIN Setting = 25% t (LFDATA output = toggled) Amplitude Demodulated LFDATA Output if MODMIN Setting = 50% (LFDATA output = not toggled) 0 t
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11.22 Low-Current Sleep Mode
The Sleep command from the microcontroller, via an SPI Interface command, places the AFE into an ultra Low-current mode. All circuits including the RF Limiter, except the minimum circuitry required to retain register memory and SPI capability, will be powered down to minimize the AFE current draw. Power-on Reset or any SPI command, other than Sleep command, is required to wake the AFE from Sleep.
11.25 Error Detection of AFE Configuration Register Data
The AFE's Configuration registers are volatile memory. Therefore, the contents of the registers can be corrupted or cleared by any electrical incidence such as battery disconnect. To ensure the data integrity, the AFE has an error detection mechanism using row and column parity bits of the Configuration register memory map. The bit 0 of each register is a row parity bit which is calculated over the eight Configuration bits (from bit 1 to bit 8). The Column Parity Register (Configuration Register 6) holds column parity bits; each bit is calculated over the respective columns (Configuration registers 0 to 5) of the Configuration bits. The STATUS register is not included for the column parity bit calculation. Parity is to be odd. The parity bit set or cleared makes an odd number of set bits. The user needs to calculate the row and column parity bits using the contents of the registers and program them. During operation, the AFE continuously calculates the row and column parity bits of the configuration memory map. If a parity error occurs, the AFE lowers the SCLK/ALERT pin (interrupting the microcontroller section) indicating the configuration memory has been corrupted or unloaded and needs to be reprogrammed. At an initial condition after a Power-On-Reset, the values of the registers are all clear (default condition). Therefore, the AFE will issue the parity bit error by lowering the SCLK/ALERT pin. If user reprograms the registers with correct parity bits, the SCLK/ALERT pin will be toggled to logic high level immediately. The parity bit errors do not change or affect the AFE's functional operation. Table 11-4 shows an example of the register values and corresponding parity bits.
11.23 Low-Current Standby Mode
The AFE is in Standby mode when no LF signal is present on the antenna inputs but the AFE is powered and ready to receive any incoming signals.
11.24 Low-Current Operating Mode
The AFE is in Low-current Operating mode when a LF signal is present on an LF antenna input and internal circuitry is switching with the received data.
TABLE 11-4:
AFE CONFIGURATION REGISTER PARITY BIT EXAMPLE
Bit 8 1 0 0 0 0 1 1 Bit 7 0 0 0 0 0 0 1 Bit 6 1 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 1 Bit 4 1 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 1 Bit 2 0 0 0 0 0 0 1 Bit 1 0 0 0 0 0 0 1 Bit 0 (Row Parity) 0 1 1 1 1 0 1
Register Name Configuration Register 0 Configuration Register 1 Configuration Register 2 Configuration Register 3 Configuration Register 4 Configuration Register 5 Configuration Register 6 (Column Parity Register)
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11.26 Factory Calibration
Microchip calibrates the AFE to reduce the device-to-device variation in standby current, internal timing and sensitivity, as well as channel-to-channel sensitivity variation.
11.28 Battery Back-up and Batteryless Operation
The device supports both battery back-up and batteryless operation by the addition of external components, allowing the device to be partially or completely powered from the field. Figure 11-8 shows an example of the external circuit for the battery back-up. Note: Voltage on LCCOM combined with coil input voltage must not exceed the maximum LC input voltage.
11.27 De-Q'ing of Antenna Circuit
When the transponder is close to the base station, the transponder coil may develop coil voltage higher than VDE_Q. This condition is called "near field". The AFE detects the strong near field signal through the AGC control, and de-Q'ing the antenna circuit to reduce the input signal amplitude.
FIGURE 11-8:
LF FIELD POWERING AND BATTERY BACK-UP EXAMPLE
VBAT
VDD RLIM DBLOCK DLIM CPOOL DFLAT1 LX Air Coil LY CY CX LCY LCX
LCZ
LZ
CZ LCCOM
DFLAT2 RCOM CCOM
Legend:
CCOM = LCCOM charging capacitor. CPOOL = Pool capacitor (or battery back-up capacitor), charges in field and powers device. DBLOCK = Battery protection from reverse charge. Schottky for low forward bias drop. DFLAT = Field rectifier diodes. DLIM = Voltage limiting diode, may be required to limit VDD voltage when in strong fields. RCOM = CCOM discharge path. RLIM = Current limiting resistor, required for air coil in strong fields.
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11.29 Demodulator
The demodulator recovers the modulation data from the received signal, containing carrier plus data, by appropriate envelope detection. The demodulator has a fast rise (charge) time (TDR) and a fall time (TDF) appropriate to an envelope of input signal (see Section 15.0 "Electrical Specifications" for TDR and TDF specifications). The demodulator contains the full-wave rectifier, low-pass filter, peak detector and data slicer.
FIGURE 11-9:
DEMODULATOR CHARGE AND DISCHARGE
Signal into LC input pins
Full-wave Rectifier output
Data Slicer output (demodulator output) TDR TDF
11.30 Power-On Reset
This circuit remains in a Reset state until a sufficient supply voltage is applied to the AFE. The Reset releases when the supply is sufficient for correct AFE operation, nominally VPOR of AFE. The Configuration registers are all cleared on a Power-on Reset. As the Configuration registers are protected by odd row and column parity, the ALERT pin will be pulled down - indicating to the microcontroller section that the AFE configuration memory is cleared and requires loading.
For a clean data output or to save operating power, the input channels can be individually enabled or disabled. If more than one channel is enabled, the output is the sum of each output of all enabled channels. There will be no valid output if all three channels are disabled. When the demodulated output is selected, the output is available in two different conditions depending on how the options of Configuration Register 0 (Register 11-1) are set: Output Enable Filter is disabled or enabled. Related Configuration register bits: * Configuration Register 1 (Register 11-2), DATOUT <8:7>: - bit 8 bit 7 0 0 1 0 0: Demodulator Output 1: Carrier Clock Output 0: RSSI Output 1: RSSI Output
11.31 LFDATA Output Selection
The LFDATA output can be configured to pass the Demodulator output, Received Signal Strength Indicator (RSSI) output, or Carrier Clock. See Configuration Register 1 (Register 11-2) for more details.
11.31.1
DEMODULATOR OUTPUT
* Configuration Register 0 (Register 11-1): all bits
The demodulator output is the default configuration of the output selection. This is the output of an envelope detection circuit. See Figure 11-9 for the demodulator output.
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Case I. When Output Enable Filter is disabled: Demodulated output is available immediately after the AGC stabilization time (TAGC). Figure 11-10 shows an example of demodulated output when the Output Enable Filter is disabled.
FIGURE 11-10:
INPUT SIGNAL AND DEMODULATOR OUTPUT WHEN THE OUTPUT ENABLE FILTER IS DISABLED
Input Signal
LFDATA Output
Case II. When Output Enable Filter is enabled: Demodulated output is available only if the incoming signal meets the enable filter timing criteria that is defined in the Configuration Register 0 (Register 11-1). If the criteria is met, the output is available after the low timing (TOEL) of the Enable Filter. Figure 11-11 and Figure 11-12 shows examples of demodulated output when the Output Enable Filter is enabled.
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FIGURE 11-11: INPUT SIGNAL AND DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED AND INPUT MEETS FILTER TIMING REQUIREMENTS)
Input Signal
LFDATA Output
FIGURE 11-12:
NO DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED BUT INPUT DOES NOT MEET FILTER TIMING REQUIREMENTS)
Input Signal
No LFDATA Output
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11.31.2 CARRIER CLOCK OUTPUT
When the Carrier Clock output is selected, the LFDATA output is a square pulse of the input carrier clock and available as soon as the AGC stabilization time (TAGC) is completed. There are two Configuration register options for the carrier clock output: (a) clock divide-by one or (b) clock divide-by four, depending on bit DATOUT<7> of Configuration Register 2 (Register 11-3). The carrier clock output is available immediately after the AGC settling time. The Output Enable Filter, AGCSIG, and MODMIN options are applicable for the carrier clock output in the same way as the demodulated output. The input channel can be individually enabled or disabled for the output. If more than one channel is enabled, the output is the sum of each output of all enabled channels. Therefore, the carrier clock output waveform is not as precise as when only one channel is enabled. It is recommended to enable one channel only if a precise output waveform is desired. There will be no valid output if all three channels are disabled. See Figure 11-13 for carrier clock output examples. Related Configuration register bits: * Configuration Register 1 (Register 11-2), DATOUT <8:7>: bit 8 bit 7 0 0 1 1 0: Demodulator Output 1: Carrier Clock Output 0: RSSI Output 1: RSSI Output
* Configuration Register 2 (Register 11-3), CLKDIV<7>: 0: Carrier Clock/1 1: Carrier Clock/4 * Configuration Register 0 (Register 11-1): all bits are affected * Configuration Register 5 (Register 11-6)
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FIGURE 11-13:
CARRIER CLOCK OUTPUT EXAMPLES (A) CARRIER CLOCK OUTPUT WITH CARRIER/1 OPTION
Carrier Clock Output
Carrier Input
(B) CARRIER CLOCK OUTPUT WITH CARRIER/4 OPTION
Carrier Clock Output
Carrier Input
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11.31.3 RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) OUTPUT FIGURE 11-14:
RSSI OUTPUT PATH An analog current is available at the LFDATA pin when the Received Signal Strength Indicator (RSSI) output is selected for the AFE's Configuration register. The analog current is linearly proportional to the input signal strength (see Figure 11-15). All timers in the circuit, such as inactivity timer, alarm timer, and AGC settling time, are disabled during the RSSI mode. Therefore, the RSSI output is not affected by the AGC settling time, and available immediately when the RSSI option is selected. The AFE enters Active mode immediately when the RSSI output is selected. The MCU I/O pin (RC3) connected to the LFDATA pin, must be set to high-impedance state during the RSSI Output mode. When the AFE receives an SPI command during the RSSI output, the RSSI mode is temporary disabled until the SPI interface communication is completed. It returns to the RSSI mode again after the SPI interface communication is completed. The AFE holds the RSSI mode until another output type is selected (CS low turns off the RSSI signal). To obtain the RSSI output for a particular input channel, or to save operating power, the input channel can be individually enabled or disabled. If more than one channel is enabled, the RSSI output is from the strongest signal channel. There will be no valid output if all three channels are disabled. Related AFE Configuration register bits: * Configuration Register 1 (Register 11-2), DATOUT<8:7>: bit 8 0 0 1 1 bit 7 0: Demodulated Output 1: Carrier Clock Output 0: RSSI Output 1: RSSI Output
RSSI Output Current Generator Current Output VDD Off if RSSI active
RC3/LFDATA/RSSI/CCLK Pin RSSIFET
RSSI Pull-down MOSFET (controlled by Config. 2, bit 8)
* Configuration Register 2 (Register 11-3), RSSIFET<8>: 0: Pull-Down MOSFET off 1: Pull-Down MOSFET on. Note: The pull-down MOSFET option is valid only when the RSSI output is selected. The MOSFET is not controllable by users when Demodulated or Carrier Clock output option is selected.
* Configuration Register 0 (Register 11-1): all bits are affected.
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FIGURE 11-15:
90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10
RSSI OUTPUT CURRENT VS. INPUT SIGNAL LEVEL EXAMPLE
RSSI Output Current (uA)
Input Voltage (VPP)
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11.31.3.1 ANALOG-TO-DIGITAL DATA CONVERSION OF RSSI SIGNAL
11.32 AFE Configuration
11.32.1 SPI COMMUNICATION
The AFE's RSSI output is an analog current. It needs an external Analog-to-Digital (ADC) data conversion device for digitized output. The ADC data conversion can be accomplished by using a stand-alone external ADC device or by firmware utilizing MCU's internal comparator along with a few external resistors and a capacitor. For slope ADC implementations, the external capacitor at the LFDATA pad needs to be discharged before data sampling. For this purpose, the internal pull-down MOSFET on the LFDATA pad can be utilized. The MOSFET can be turned on or off with bit RSSIFET<8> of the Configuration Register 2 (Register 11-3). When it is turned on, the internal MOSFET provides a discharge path for the external capacitor. This MOSFET option is valid only if RSSI output is selected and not controllable by users for demodulated or carrier clock output options. See separate application notes for various external ADC implementation methods for this device.
The AFE SPI interface communication is used to read or write the AFE's Configuration registers and to send command only messages. For the SPI interface, the device has three pads; CS, SCLK/ALERT, and LFDATA/RSSI/CCLK/SDIO. Figure 11-15, Figure 11-14, Figure 11-16 and Figure 11-17 shows examples of the SPI communication sequences. When the device powers up, these pins will be high-impedance inputs until firmware modifies them appropriately. The AFE pins connected to the MCU pins will be as follows. CS * Pin is permanently an input with an internal pull-up. SCLK/ALERT * Pin is an open collector output when CS is high. An internal pull-up resistor exists internal to the AFE to ensure no spurious SPI communication between powering and the MCU configuring its pins. This pin becomes the SPI clock input when CS is low. LFDATA/RSSI/CCLK/SDIO * Pin is a digital output (LFDATA) so long as CS is high. During SPI communication, the pin is the SPI data input (SDI) unless performing a register Read, where it will be the SPI data output (SDO).
FIGURE 11-16:
POWER-UP SEQUENCE
MCU pin is input. CS pulled high by internal pull-up Driving CS high MCU pin output
CS
SCLK/ALERT
LFDATA/RSSI/ CCLK/SDIO
MCU pin is input.
LFDATA (output)
by internal pull-up ALERT (open collector output)
MCU pin is input. SCLK pulled high
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FIGURE 11-17: SPI WRITE SEQUENCE
TCSH 2 CS TCSSC Driven low by MCU TSCCS TCS1 Driven low by MCU 7 6 MCU pin to Input
SCLK/ ALERT ALERT (output)
SCLK (input)
MSb 1/FSCLK
LSb
ALERT (output)
1 MCU pin still Input
LFDATA/RSSI/ CCLK/SDIO LFDATA (output)
SDI (input) 3
MCU pin to Output
MCU pin to Input
TSU
THD
5
LFDATA (output)
MCU SPI Write Details: 1. 2. Drive the AFE's open collector ALERT output low. * To ensure no false clocks occur when CS drops. Drop CS. * AFE SCLK/ALERT becomes SCLK input. * LFDATA/RSSI/CCLK/SDIO becomes SDI input. Change LFDATA/RSSI/CCLK/SDIO connected pin to output. * Driving SPI data. Clock in 16-bit SPI Write sequence - command, address, data and parity bit. * Command, address, data and parity bit. Change LFDATA/RSSI/CCLK/SDIO connected pin to input. Raise CS to complete the SPI Write. Change SCLK/ALERT back to input.
3. 4. 5. 6. 7.
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Driven low by MCU
4 16 Clocks for Write Command, Address and Data THI TLO
TCS0
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FIGURE 11-18: SPI READ SEQUENCE
TCSH 2 6 MCU pin to Input 7 9
TCSH
TCSSC
4
16 Clocks for Read Command, Address and Dummy Data THI TLO
TSCCS TCS1
TCS0
TCSSC
8 16 Clocks for Read Result
10 TCSSC TCS1
MCU pin to Input
CS
TCS0 Driven low by MCU
Driven low by MCU
SCLK/ALERT ALERT (output)
SCLK (input)
MSb 1/FSCLK
LSb ALERT (output)
SCLK (input)
Driven low by MCU TDO
Driven low by MCU
ALERT (output)
1 MCU pin still Input
TSU THD MCU pin to Output MCU pin to Input 3 5 LFDATA (output)
LFDATA/RSSI/ CCLK/SDIO LFDATA (output)
SDI (input)
SDO (output)
LFDATA (output)
MCU SPI Read Details: 1. 2. Drive the AFE's open collector ALERT output low. * To ensure no false clocks occur when CS drops. Drop CS * AFE SCLK/ALERT becomes SCLK input. * LFDATA/RSSI/CCLK/SDIO becomes SDI input. Change LFDATA/RSSI/CCLK/SDIO connected pin to output. * Driving SPI data. Clock in 16-bit SPI Read sequence. * Command, address and dummy data. Change LFDATA/RSSI/CCLK/SDIO connected pin to input. Raise CS to complete the SPI Read entry of command and address. The TCSH is considered as one clock. Therefore, the Configuration register data appears at 6th clock after TCSH. 7. Drop CS. * AFE SCLK/ALERT becomes SCLK input. * LFDATA/RSSI/CCLK/SDIO becomes SDO output. Clock out 16-bit SPI Read result. * First seven bits clocked-out are dummy bits. * Next eight bits are the Configuration register data. * The last bit is the Configuration register row parity bit. Raise CS to complete the SPI Read. Change SCLK/ALERT back to input.
8.
3. 4. 5. 6.
9. 10.
Note:
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11.32.2 COMMAND DECODER/CONTROLLER
The circuit executes 8 SPI commands from the MCU. The command structure is: Command (3 bits) + Configuration Address (4 bits) + Data Byte and Row Parity Bit received by the AFE Most Significant bit first. Table 11-5 shows the available SPI commands. The AFE operates in SPI mode 0,0. In mode 0,0 the clock idles in the low state (Figure 11-19). SDI data is loaded into the AFE on the rising edge of SCLK and SDO data is clocked out on the falling edge of SCLK. There must be multiples of 16 clocks (SCLK) while CS is low or commands will abort.
TABLE 11-5:
SPI COMMANDS (AFE)
Data Row Parity X X X X X X P P P P P P P X P P P P P P P X Description
Command Address
Command only - Address and Data are "Don't Care", but need to be clocked in regardless. 000 001 010 011 100 101 110 XXXX XXXX XXXX XXXX XXXX XXXX 0000 0001 0010 0011 0100 0101 0110 0111 111 0000 0001 0010 0011 0100 0101 0110 0111 Note: XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX Config Byte 0 Config Byte 1 Config Byte 2 Config Byte 3 Config Byte 4 Config Byte 5 Column Parity AFE Status Config Byte 0 Config Byte 1 Config Byte 2 Config Byte 3 Config Byte 4 Config Byte 5 Column Parity Not Used Clamp on - enable modulation circuit Clamp off - disable modulation circuit Enter Sleep mode (any other command wakes the AFE) AGC Preserve On - to temporarily preserve the current AGC level AGC Preserve Off - AGC again tracks strongest input signal Soft Reset - resets various circuit blocks General - options that may change during normal operation LCX antenna tuning and LFDATA output format LCY antenna tuning LCZ antenna tuning LCX and LCY sensitivity reduction LCZ sensitivity reduction and modulation depth Column parity byte for Config Byte 0 -> Config Byte 5 AFE status - parity error, which input is active, etc. General - options that may change during normal operation LCX antenna tuning and LFDATA output format LCY antenna tuning LCZ antenna tuning LCX and LCY sensitivity reduction LCZ sensitivity reduction and modulation depth Column parity byte for Config Byte 0 -> Config Byte 5 Register is readable, but not writable
Read Command - Data will be read from the specified register address.
Write Command - Data will be written to the specified register address.
`P' denotes the row parity bit (odd parity) for the respective data byte.
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FIGURE 11-19:
CS 1 SCLK MSb SDIO bit 2 bit 0 bit 3 bit 0 bit 7 bit 0 Data Byte Row Parity Bit LSb 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DETAILED SPI INTERFACE TIMING (AFE)
Command
Address
11.32.2.1
Clamp On Command
11.32.2.5
AGC Preserve On Command
This command results in activating (turning on) the modulation transistors of all enabled channels; channels enabled in Configuration Register 0 (Register 11-1).
11.32.2.2
Clamp Off Command
This command results in de-activating (turning off) the modulation transistors of all channels.
This command results in preserving the AGC level during each AGC settling time and apply the value to the data slicing circuit for the following data stream. The preserved AGC value is reset by a Soft Reset, and a new AGC value is acquired and preserved when it starts a new AGC settling time. This feature is disabled by an AGC Preserve Off command (see Section 11.19 "AGC Preserve").
11.32.2.3
Sleep Command
This command places the AFE in Sleep mode - minimizing current draw by disabling all but the essential circuitry. Any other command wakes the AFE (example: Clamp Off command).
11.32.2.6
AGC Preserve Off Command
This command disables the AGC preserve feature and returns the AFE to the normal AGC tracking mode, fast tracking during AGC settling time and slow tracking after that (see Section 11.19 "AGC Preserve").
11.32.2.4
Soft Reset Command
The AFE issues a Soft Reset when it receives an external Soft Reset command. The external Soft Reset command is typically used to end a SPI communication sequence or to initialize the AFE for the next signal detection sequence, etc. See Section 11.20 "Soft Reset" for more details on Soft Reset. If a Soft Reset command is sent during a "Clamp-on" condition, the AFE still keeps the "Clamp-on" condition after the Soft Reset execution. The Soft Reset is executed in Active mode only, not in Standby mode. The SPI Soft Reset command is ignored if the AFE is not in Active mode.
11.32.3
CONFIGURATION REGISTERS
The AFE includes 8 Configuration registers, including a column parity register and AFE Status Register. All registers are readable and writable via SPI, except STATUS register, which is readable only. Bit 0 of each register is a row parity bit (except for the AFE Status Register 7) that makes the register contents an odd number.
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TABLE 11-6:
Register Name Configuration Register 0 Configuration Register 1 Configuration Register 2 Configuration Register 3 Configuration Register 4 Configuration Register 5 Column Parity Register 6 AFE Status Register 7
ANALOG FRONT-END CONFIGURATION REGISTERS SUMMARY
Address 0000 0001 0010 0011 0100 0101 0110 0111 Active Channel Indicators Bit 8 OEH DATOUT RSSIFET CLKDIV Bit 7 Bit 6 OEL Bit 5 Bit 4 ALRTIND Bit 3 LCZEN Bit 2 LCYEN Bit 1 LCXEN Bit 0 R0PAR R1PAR R2PAR R3PAR R4PAR R5PAR R6PAR ALARM PEI
Channel X Tuning Capacitor Channel Y Tuning Capacitor Channel Z Tuning Capacitor Channel Y Sensitivity Control MODMIN Column Parity Bits AGCACT Wake-up Channel Indicators Channel Z Sensitivity Control
Unimplemented Channel X Sensitivity Control AUTOCHSEL AGCSIG MODMIN
REGISTER 11-1:
R/W-0 OEH1 bit 8 Legend: R = Readable bit -n = Value at POR bit 8-7 R/W-0 OEH0
CONFIGURATION REGISTER 0
R/W-0 OEL1 R/W-0 OEL0 R/W-0 ALRTIND R/W-0 LCZEN R/W-0 LCYEN R/W-0 LCXEN R/W-0 R0PAR bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OEH<1:0>: Output Enable Filter High Time (TOEH) bit 00 = Output Enable Filter disabled (no wake-up sequence required, passes all signal to LFDATA) 01 = 1 ms 10 = 2 ms 11 = 4 ms OEL<1:0>: Output Enable Filter Low Time (TOEL) bit 00 = 1 ms 01 = 1 ms 10 = 2 ms 11 = 4 ms ALRTIND: ALERT bit, output triggered by: 1 = Parity error and/or expired Alarm timer (receiving noise, see Section 11.14.3 "Alarm Timer") 0 = Parity error LCZEN: LCZ Enable bit 1 = Disabled 0 = Enabled LCYEN: LCY Enable bit 1 = Disabled 0 = Enabled LCXEN: LCX Enable bit 1 = Disabled 0 = Enabled R0PAR: Register Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 11-2:
R/W-0 DATOUT1 bit 8 Legend: R = Readable bit -n = Value at POR bit 8-7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CONFIGURATION REGISTER 1
R/W-0 LCXTUN5 R/W-0 LCXTUN4 R/W-0 LCXTUN3 R/W-0 LCXTUN2 R/W-0 LCXTUN1 R/W-0 LCXTUN0 R/W-0 R1PAR bit 0
R/W-0 DATOUT0
DATOUT<1:0>: LFDATA Output type bit 00 = Demodulated output 01 = Carrier Clock output 10 = RSSI output 11 = RSSI output LCXTUN<5:0>: LCX Tuning Capacitance bit 000000 = +0 pF (Default) : 111111 = +63 pF R1PAR: Register Parity Bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits
bit 6-1
bit 0
REGISTER 11-3:
R/W-0 RSSIFET bit 8 Legend: R = Readable bit -n = Value at POR bit 8
CONFIGURATION REGISTER 2
R/W-0 LCYTUN5 R/W-0 LCYTUN4 R/W-0 LCYTUN3 R/W-0 LCYTUN2 R/W-0 LCYTUN1 R/W-0 LCYTUN0 R/W-0 R2PAR bit 0
R/W-0 CLKDIV
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RSSIFET: Pull-down MOSFET on LFDATA pad bit (controllable by user in the RSSI mode only) 1 = Pull-down RSSI MOSFET on 0 = Pull-down RSSI MOSFET off CLKDIV: Carrier Clock Divide-by bit 1 = Carrier Clock/4 0 = Carrier Clock/1 LCYTUN<5:0>: LCY Tuning Capacitance bit 000000 = +0 pF (Default) : 111111 = +63 pF R2PAR: Register Parity Bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits
bit 7
bit 6-1
bit 0
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REGISTER 11-4:
U-0 -- bit 8 Legend: R = Readable bit -n = Value at POR bit 8-7 bit 6-1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 --
CONFIGURATION REGISTER 3
R/W-0 LCZTUN5 R/W-0 LCZTUN4 R/W-0 LCZTUN3 R/W-0 LCZTUN2 R/W-0 LCZTUN1 R/W-0 LCZTUN0 R/W-0 R3PAR bit 0
Unimplemented: Read as `0' LCZTUN<5:0>: LCZ Tuning Capacitance bit 000000 = +0 pF (Default) : 111111 = +63 pF R3PAR: Register Parity Bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits
bit 0
REGISTER 11-5:
R/W-0 LCXSEN3 bit 8 Legend: R = Readable bit -n = Value at POR bit 8-5
CONFIGURATION REGISTER 4
R/W-0 LCXSEN1 R/W-0 LCXSEN0 R/W-0 LCYSEN3 R/W-0 LCYSEN2 R/W-0 LCYSEN1 R/W-0 LCYSEN0 R/W-0 R4PAR bit 0
R/W-0 LCXSEN2
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
LCXSEN<3:0>(1): Typical LCX Sensitivity Reduction bit 0000 = -0 dB (Default) 0001 = -2 dB 0010 = -4 dB 0011 = -6 dB 0100 = -8 dB 0101 = -10 dB 0110 = -12 dB 0111 = -14 dB 1000 = -16 dB 1001 = -18 dB 1010 = -20 dB 1011 = -22 dB 1100 = -24 dB 1101 = -26 dB 1110 = -28 dB 1111 = -30 dB LCYSEN<3:0>(1): Typical LCY Sensitivity Reduction bit 0000 = -0 dB (Default) : 1111 = -30 dB R4PAR: Register Parity Bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits Assured monotonic increment (or decrement) by design.
bit 4-1
bit 0 Note 1:
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REGISTER 11-6:
R/W-0 AUTOCHSEL bit 8 Legend: R = Readable bit -n = Value at POR bit 8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CONFIGURATION REGISTER 5
R/W-0 MODMIN1 R/W-0 MODMIN0 R/W-0 LCZSEN3 R/W-0 LCZSEN2 R/W-0 LCZSEN1 R/W-0 LCZSEN0 R/W-0 R5PAR bit 0
R/W-0 AGCSIG
AUTOCHSEL: Auto Channel Select bit 1 = Enabled - AFE selects channel(s) that has demodulator output "high" at the end of TSTAB; or otherwise, blocks the channel(s). 0 = Disabled - AFE follows channel enable/disable bits defined in Register 0 AGCSIG: Demodulator Output Enable bit, after the AGC loop is active 1 = Enabled - No output until AGC is regulating at around 20 mVPP at input pins. The AGC Active Status bit is set when the AGC begins regulating. 0 = Disabled - the AFE passes signal of any level it is capable of detecting MODMIN<1:0>: Minimum Modulation Depth bit 00 = 50% 01 = 75% 10 = 25% 11 = 12% LCZSEN<3:0>(1): LCZ Sensitivity Reduction bit 0000 = -0dB (Default) : 1111 = -30dB R5PAR: Register Parity Bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits 1: Assured monotonic increment (or decrement) by design.
bit 7
bit 6-5
bit 4-1
bit 0 Note
REGISTER 11-7:
R/W-0 COLPAR7 bit 8 Legend: R = Readable bit -n = Value at POR bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
COLUMN PARITY REGISTER 6
R/W-0 COLPAR5 R/W-0 COLPAR4 R/W-0 COLPAR3 R/W-0 COLPAR2 R/W-0 COLPAR1 R/W-0 COLPAR0 R/W-0 R6PAR bit 0
R/W-0 COLPAR6
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the Configuration register row parity bits contain an odd number of set bits. COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in Configuration Registers 0 through 5 contain an odd number of set bits. COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in Configuration Registers 0 through 5 contain an odd number of set bits. COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in Configuration Registers 0 through 5 contain an odd number of set bits. COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in Configuration Registers 0 through 5 contain an odd number of set bits. COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in Configuration Registers 0 through 5 contain an odd number of set bits. COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in Configuration Registers 0 through 5 contain an odd number of set bits. COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in Configuration Registers 0 through 5 contain an odd number of set bits. R6PAR: Register Parity bit - set/cleared so the 9-bit register contains odd parity - an odd number of set bits
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REGISTER 11-8:
R-0 CHZACT bit 8 Legend: R = Readable bit -n = Value at POR bit 8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 CHYACT
AFE STATUS REGISTER 7
R-0 CHXACT R-0 AGCACT R-0 WAKEZ R-0 WAKEY R-0 WAKEX R-0 ALARM R-0 PEI bit 0
CHZACT: Channel Z Active(1) bit (cleared via Soft Reset) 1 = Channel Z is passing data after TAGC 0 = Channel Z is not passing data after TAGC CHYACT: Channel Y Active(1) bit (cleared via Soft Reset) 1 = Channel Y is passing data after TAGC 0 = Channel Y is not passing data after TAGC CHXACT: Channel X Active(1) bit (cleared via Soft Reset) 1 = Channel X is passing data after TAGC 0 = Channel X is not passing data after TAGC AGCACT: AGC Active Status bit (real time, cleared via Soft Reset) 1 = AGC is active (Input signal is strong). AGC is active when input signal level is approximately > 20 mVPP range. 0 = AGC is inactive (Input signal is weak) WAKEZ: Wake-up Channel Z Indicator Status bit (cleared via Soft Reset) 1 = Channel Z caused a AFE wake-up (passed /64 clock counter) 0 = Channel Z did not cause a AFE wake-up WAKEY: Wake-up Channel Y Indicator Status bit (cleared via Soft Reset) 1 = Channel Y caused a AFE wake-up (passed /64 clock counter) 0 = Channel Y did not cause a AFE wake-up WAKEX: Wake-up Channel X Indicator Status bit (cleared via Soft Reset) 1 = Channel X caused a AFE wake-up (passed /64 clock counter) 0 = Channel X did not cause a AFE wake-up ALARM: Indicates whether an Alarm timer time-out has occurred (cleared via read "Status Register command") 1 = The Alarm timer time-out has occurred. It may cause the ALERT output to go low depending on the state of bit 4 of the Configuration register 0 0 = The Alarm timer is not timed out PEI: Parity Error Indicator bit - indicates whether a Configuration register parity error has occurred (real time) 1 = A parity error has occurred and caused the ALERT output to go low 0 = A parity error has not occurred 1: Bit is high whenever channel is passing data. Bit is low in Standby mode.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note
See Table 11-7 for the bit conditions of the AFE Status Register after various SPI commands and the AFE Power-on Reset.
TABLE 11-7:
AFE STATUS REGISTER BIT CONDITION (AFTER POWER-ON RESET AND VARIOUS SPI COMMANDS)
Bit 8 Bit 7 CHYACT 0 u u 0 Bit 6 CHXACT 0 u u 0 Bit 5 AGCACT 0 u u 0 Bit 4 WAKEZ 0 u u 0 Bit 3 WAKEY 0 u u 0 Bit 2 WAKEX 0 u u 0 Bit 1 ALARM 0 0 u u Bit 0 PEI 1 u u u
Condition CHZACT POR Read Command (STATUS Register only) Sleep Command Soft Reset Executed(1) Legend: Note 1: 0 u u 0
u = unchanged See Section 11.20 "Soft Reset" and Section 11.32.2.4 "Soft Reset Command" for the condition of Soft Reset execution.
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NOTES:
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12.0 SPECIAL FEATURES OF THE CPU
12.1 Configuration Bits
The Configuration Word bits can be programmed (read as `0'), or left unprogrammed (read as `1') to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h3FFFh), which can be accessed only during programming. See "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information.
The PIC12F635/PIC16F636/639 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: * Reset - Power-on Reset (POR) - Wake-up Reset (WUR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Oscillator selection * Sleep * Code protection * ID Locations * In-Circuit Serial ProgrammingTM The PIC12F635/PIC16F636/639 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power-up Timer to provide at least a nominal 64 ms Reset. With these three functions on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-down mode. The user can wake-up from Sleep through: * External Reset * Watchdog Timer Wake-up * An Interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 12-1).
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REGISTER 12-1:
-- bit 15
CONFIG: CONFIGURATION WORD REGISTER
-- --
WURE
FCMEN
IESO
BOREN1
BOREN0 bit 8
CPD bit 7
Legend: R = Readable bit -n = Value at POR
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0 bit 0
W = Writable bit `1' = Bit is set
P = Programmable' `0' = Bit is cleared
U = Unimplemented bit, read as `0' x = Bit is unknown
bit 15-13 bit 12
Unimplemented: Read as `1' WURE: Wake-up Reset Enable bit 1 = Standard wake-up and continue enabled 0 = Wake-up and Reset enabled FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled 0 = Internal External Switchover mode is disabled BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled, SBOREN bit disabled 10 = BOR enabled during operation and disabled in Sleep, SBOREN bit disabled 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR and SBOREN bits disabled CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled MCLRE: MCLR pin function select bit(4) 1 = MCLR pin function is MCLR 0 = MCLR pin function is digital input, MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled and can be enabled by SWDTEN bit of the WDTCON register FOSC<2:0>: Oscillator Selection bits 111 = EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin 110 = EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin 101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN 011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off. The entire program memory will be erased when the code protection is turned off. When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1: 2: 3: 4:
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12.2 Reset
The PIC12F635/PIC16F636/639 differentiates between various kinds of Reset: a) b) c) d) e) f) g) Power-on Reset (POR) Wake-up Reset (WUR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 12-3. These bits are used in software to determine the nature of the Reset. See Table 12-4 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 12-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 15.0 "Electrical Specifications" for pulse width specifications.
Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on: * * * * * Power-on Reset MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Reset
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Sleep WURE Wake-up Interrupt
External Reset MCLR/VPP pin WDT Module VDD Rise Detect VDD Brown-out(1) Reset BOREN BOREN<0> SBOREN <1> Power-on Reset Sleep WDT Time-out Reset
RA3 Change
S
OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKI pin PWRT LFINTOSC 11-bit Ripple Counter R Q Chip_Reset
Enable PWRT Enable OST Note 1: Refer to the Configuration Word register (Register 12-1).
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12.3 Power-on Reset
12.4.1 POWER-UP TIMER (PWRT)
The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 15.0 "Electrical Specifications" for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOD (see Section 12.6 "Brown-out Reset (BOR)"). Note: The POR circuit does not produce an internal Reset when VDD declines. To re-enable the POR, VDD must reach VSS for a minimum of 100 s. The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from the 31 kHz LFINTOSC oscillator. For more information, see Section 3.5 "Internal Clock Modes". The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip due to: * VDD variation * Temperature variation * Process variation See DC parameters for details "Electrical Specifications"). (Section 15.0
When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to the Application Note AN607, "Power-up Trouble Shooting" (DS00607).
Note:
12.4
Wake-up Reset (WUR)
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling this pin directly to VSS.
The PIC12F635/PIC16F636/639 has a modified wake-up from Sleep mechanism. When waking from Sleep, the WUR function resets the device and releases Reset when VDD reaches an acceptable level. If the WURE bit is enabled (`0') in the Configuration Word register, the device will Wake-up Reset from Sleep through one of the following events: 1. On any event that causes a wake-up event. The peripheral must be enabled to generate an interrupt or wake-up, GIE state is ignored. When WURE is enabled, RA3 will always generate an interrupt-on-change signal during Sleep.
12.5
MCLR
PIC12F635/PIC16F636/639 has a noise filter in the MCLR Reset path. The filter will ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. See Figure 12-2 for the recommended MCLR circuit. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When cleared, MCLR is internally tied to VDD and an internal weak pull-up is enabled for the MCLR pin. In-Circuit Serial Programming is not affected by selecting the internal MCLR option.
2.
The WUR, POR and BOR bits in the PCON register and the TO and PD bits in the STATUS register can be used to determine the cause of device Reset. To allow WUR upon RA3 change: 1. 2. 3. 4. 5. Enable the WUR function, WURE Configuration Bit = 0. Enable RA3 as an input, MCLRE Configuration Bit = 0. Read PORTA to establish the current state of RA3. Execute SLEEP instruction. When RA3 changes state, the device will wake-up and then reset. The WUR bit in PCON will be cleared to `0'.
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FIGURE 12-2:
VDD R1 1 k (or greater) PIC12F635/PIC16F636/639
RECOMMENDED MCLR CIRCUIT
MCLR C1 0.1 F (optional, not critical)
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12.6 Brown-out Reset (BOR)
The BOREN0 and BOREN1 bits in the Configuration Word register select one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit of the PCON register enables/disables the BOR allowing it to be controlled in software. By selecting BOREN<1:0>, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. In this mode, the SBOREN bit is disabled. See Register 12-1 for the Configuration Word definition. If VDD falls below VBOD for greater than parameter (TBOD) (see Section 15.0 "Electrical Specifications"), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not ensured to occur if VDD falls below VBOD for less than parameter (TBOD). On any Reset (Power-on, Brown-out Reset, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises above VBOD (see Figure 12-3). The Power-up Timer will now be invoked, if enabled and will keep the chip in Reset an additional nominal 64 ms. Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word register.
If VDD drops below VBOD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOD, the Power-up Timer will execute a 64 ms Reset.
FIGURE 12-3:
BROWN-OUT RESET SITUATIONS
VDD VBOD
Internal Reset VDD
64 ms(1)
VBOD < 64 ms
Internal Reset
64 ms(1)
VDD
VBOD
Internal Reset Note 1:
64 ms(1) Nominal 64 ms delay only if PWRTE bit is programmed to `0'.
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12.7 Time-out Sequence 12.8 Power Control (PCON) Register
On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator Configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 12-4, Figure 12-5 and Figure 12-6 depict time-out sequences. The device can execute code from the INTOSC, while OST is active, by enabling Two-Speed Start-up or Fail-Safe Clock Monitor (See Section 3.7.2 "Two-Speed Start-up Sequence" and Section 3.8 "Fail-Safe Clock Monitor"). Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F635/PIC16F636/639 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers. The Power Control register, PCON (address 8Eh), has two Status bits to indicate what type of Reset that last occurred. Bit 0 is BOR (Brown-out). BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register). Bit 1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent Reset, if POR is `0', it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 4.2.3 "Ultra Low-Power Wake-up" and Section 12.6 "Brown-out Reset (BOR)".
TABLE 12-1:
Oscillator Configuration XT, HS, LP RC, EC, INTOSC
TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC -- Brown-out Reset PWRTE = 0 TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC -- Wake-up from Sleep 1024 * TOSC --
TABLE 12-2:
Name CONFIG(2) PCON STATUS Legend: Note 1: 2: Bit 9
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR -- --01 --qq 0001 1xxx Value on all other Resets(1) -- --0u --uu 000q quuu
BOREN1
BOREN0
CPD -- IRP
CP -- RP1
MCLRE
PWRTE
WDTE WUR PD
FOSC2 -- Z
FOSC1 POR DC
FOSC0 BOR C
ULPWUE SBOREN RP0 TO
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by BOR. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. See Configuration Word register (Register 12-1) for operation of all register bits.
TABLE 12-3:
POR 0 u u u u u u u x 0 u u u u u 0
PCON BITS AND THEIR SIGNIFICANCE
WUR x u u u u u 0 u TO 1 1 0 0 u 1 1 1 PD 1 1 u 0 u 0 0 1 Power-on Reset Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep Wake-up Reset during Sleep Brown-out Reset during Sleep Condition
BOR
Legend: u = unchanged, x = unknown
(c) 2007 Microchip Technology Inc.
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FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD MCLR Internal POR TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-6:
VDD MCLR Internal POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
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TABLE 12-4:
Register
INITIALIZATION CONDITION FOR REGISTERS
Address Power-on Reset Wake-up Reset xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx xx00 --xx xx00 ---0 0000 0000 000x 0000 00-0 xxxx xxxx xxxx xxxx 0000 0000 ---0 1000 0000 0000 ---- --10 1111 1111 --11 1111 --11 1111 0000 00-0 --01 q-qq -110 q000 ---0 0000 --11 -111 --00 0000 --11 -111 0-0- 0000 0000 0000 0000 0000 ---- x000 ---- ---xxxx xxxx -000 -----00 -000 00-- --00 MCLR Reset WDT Reset Brown-out Reset(1) Wake-up Reset uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 000q quuu
(4)
Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu --uu uu00 --uu uu00 ---u uuuu uuuu uuuu(2) uuuu uu-u(2) uuuu uuuu uuuu uuuu -uuu uuuu ---u uuuu uuuu uuuu ---- --uu uuuu uuuu --uu 1uuu --uu 1uuu uuuu uu-u --0u u-uu -uuu uuuu ---u uuuu uuuu uuuu --uu uuuu uuuu uuuu u-u- uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- ---uuuu uuuu -uuu -----uu -uuu uu-- --uu
W INDF TMR0 PCL STATUS FSR PORTA PORTC(6) PCLATH INTCON PIR1 TMR1L TMR1H T1CON WDTCON CMCON0 CMCON1 OPTION_REG TRISA TRISC PIE1 PCON OSCCON OSCTUNE WPUDA IOCA WDA VRCON EEDAT EEADR EECON1 EECON2 ADRESL ADCON1 LVDCON CRCON Legend: Note 1: 2: 3: 4: 5: 6:
(6)
-- 00h/80h 01h 02h/82h 03h/83h 04h/84h 05h 07h 0Ah/8Ah 0Bh/8Bh 0Ch 0Eh 0Fh 10h 18h 19h 1Ah 81h 85h 87h 8Ch 8Eh 8Fh 90h 95h 96h 97h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh 94h 110h
uuuu uuuu --00 0000 --00 0000 ---0 0000 0000 000x 0000 00-0 uuuu uuuu uuuu uuuu uuuu uuuu ---0 1000 0000 0000 ---- --10 1111 1111 --11 1111 --11 1111 0000 00-0 --0u u-uu
(1,5)
-110 q000 ---u uuuu --11 -111 --00 0000 --11 -111 0-0- 0000 0000 0000 0000 0000 ---- q000 ---- ---uuuu uuuu -000 -----00 -000 00-- --00
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 12-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. PIC16F636/639 only.
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TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep Wake-up Reset Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1(1) 000h Status Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1uuu uuu1 0uuu 0001 1xxx PCON Register --01 --0x --0u --uu --0u --uu --0u --uu --uu --uu --01 --10 --uu --uu --01 --0x
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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12.9 Interrupts
The PIC12F635/PIC16F636/639 has multiple interrupt sources: * * * * * * * External Interrupt RA2/INT Timer0 Overflow Interrupt PORTA Change Interrupts 2 Comparator Interrupts Timer1 Overflow Interrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt For external interrupt events, such as the INT pin or PORTA change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 12-8). The latency is the same for one or two-cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. For additional information on Timer1, comparators or data EEPROM modules, refer to the respective peripheral section.
The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. A Global Interrupt Enable bit GIE of the INTCON register enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIE1 register. GIE is cleared on Reset. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: * INT Pin Interrupt * PORTA Change Interrupt * TMR0 Overflow Interrupt The peripheral interrupt flags are contained in the special register, PIR1. The corresponding interrupt enable bit is contained in special register, PIE1. The following interrupt flags are contained in the PIR1 register: * * * * EEPROM Data Write Interrupt 2 Comparator Interrupts Timer1 Overflow Interrupt Fail-Safe Clock Monitor Interrupt
12.9.1
RA2/INT INTERRUPT
External interrupt on RA2/INT pin is edge-triggered; either rising if the INTEDG bit of the OPTION register is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RA2/INT pin, the INTF bit of the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON register. The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The RA2/INT interrupt can wake-up the processor from Sleep if the INTE bit was set prior to going into Sleep. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). See Section 12.12 "Power-Down Mode (Sleep)" for details on Sleep and Figure 12-10 for timing of wake-up from Sleep through RA2/INT interrupt. Note: The CMCON0 (19h) register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
When an interrupt is serviced: * The GIE is cleared to disable any further interrupt. * The return address is pushed onto the stack. * The PC is loaded with 0004h.
(c) 2007 Microchip Technology Inc.
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12.9.2 TIMER INTERRUPT 12.9.3 PORTA INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 5.0 "Timer0 Module" for operation of the Timer0 module. An input change on PORTA change sets the RAIF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing the RAIE bit of the INTCON register. Plus, individual pins can be configured through the IOCA register. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RAIF interrupt flag may not get set.
FIGURE 12-7:
INTERRUPT LOGIC
IOC-RA0 IOCA0 IOC-RA1 IOCA1 IOC-RA2 IOCA2 IOC-RA3 IOCA3 IOC-RA4 IOCA4 IOC-RA5 IOCA5 LVDIF LVDIE TMR1IF TMR1IE C1IF C1IE C2IF(1) (1) C2IE EEIF EEIE OSFIF OSFIE CRIF CRIE T0IF T0IE INTF INTE RAIF RAIE PEIE GIE Wake-up (If in Sleep mode)
Interrupt to CPU
Note 1:
PIC16F636/639 only.
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FIGURE 12-8:
Q1 OSC1 CLKOUT(3) INT pin
(1) (4)
INT PIN INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(1) (5)
INTF Flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5:
Interrupt Latency(2)
PC Inst (PC) Inst (PC - 1)
PC + 1 Inst (PC + 1) Inst (PC)
PC + 1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKOUT is available only in INTOSC and RC Oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 15.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 12-6:
Name INTCON IOCA PIR1 PIE1
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 6 PEIE -- LVDIF LVDIE Bit 5 T0IE IOCA5 CRIF CRIE Bit 4 INTE IOCA4 C2IF(1) C2IE(1) Bit 3 RAIE IOCA3 C1IF C1IE Bit 2 T0IF IOCA2 OSFIF OSFIE Bit 1 INTF IOCA1 -- -- Bit 0 RAIF IOCA0 TMR1IF Value on: POR, BOR Value on all other Resets
Bit 7 GIE -- EEIF EEIE
0000 000x 0000 000x --00 0000 --00 0000 0000 00-0 0000 00-0
TMR1IE 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0', q = value depends upon condition. Shaded cells are not used by the Interrupt module. Note 1: PIC16F636/639 only.
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12.10 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC12F635/PIC16F636/639 (see Figure 2-2), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, make it easier to context save and restore. The same code shown in Example 12-1 can be used to: * * * * * Store the W register. Store the STATUS register. Execute the ISR code. Restore the Status (and Bank Select Bit register). Restore the W register. Note: The PIC12F635/PIC16F636/639 normally does not require saving the PCLATH. However, if computed GOTO's are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR.
EXAMPLE 12-1:
MOVWF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
;Copy W to TEMP ;Swap status to ;Swaps are used ;Save status to register be saved into W because they do not affect the status bits bank zero STATUS_TEMP register
W_TEMP STATUS,W
MOVWF STATUS_TEMP : :(ISR) : SWAPF STATUS_TEMP,W MOVWF SWAPF SWAPF STATUS W_TEMP,F W_TEMP,W
;Insert user code here ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
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12.11 Watchdog Timer (WDT)
The PIC12F635/PIC16F636/639 WDT is code and functionally compatible with other PIC16F WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaler value for the WDT and TMR0 at the same time. In addition, the WDT time-out value can be extended to 268 seconds. WDT is cleared under certain conditions described in Table 12-7. A new prescaler has been added to the path between the INTRC and the multiplexers used to select the path for the WDT. This prescaler is 16 bits and can be programmed to divide the INTRC by 32 to 65536, giving the WDT a nominal range of 1 ms to 268s.
12.11.2
WDT CONTROL
The WDTE bit is located in the Configuration Word register. When set, the WDT runs continuously. When the WDTE bit in the Configuration Word register is set, the SWDTEN bit of the WDTCON register has no effect. If WDTE is clear, then the SWDTEN bit can be used to enable and disable the WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits of the OPTION register have the same function as in previous versions of the PIC16F family of microcontrollers. See Section 5.0 "Timer0 Module" for more information.
12.11.1
WDT OSCILLATOR
The WDT derives its time base from the 31 kHz LFINTOSC. The LTS bit does not reflect that the LFINTOSC is enabled. The value of WDTCON is `---0 1000' on all Resets. This gives a nominal time base of 16 ms, which is compatible with the time base generated with previous PIC12F635/PIC16F636/639 microcontroller versions. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled).
FIGURE 12-9:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source 0 Prescaler(1)
16-bit WDT Prescaler
1
8 PSA 31 kHz LFINTOSC Clock
PS<2:0> To TMR0 0 1 PSA
WDTPS<3:0>
WDTE from Configuration Word Register SWDTEN from WDTCON WDT Time-out Note 1: This is the shared Timer0/WDT prescaler. See Section 5.1.3 "Software Programmable Prescaler" for more information.
TABLE 12-7:
WDTE = 0
WDT STATUS
Conditions WDT
CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, HFINTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP
Cleared
Cleared until the end of OST
(c) 2007 Microchip Technology Inc.
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REGISTER 12-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 -- U-0 -- R/W-0 WDTPS3 R/W-1 WDTPS2 R/W-0 WDTPS1 R/W-0 WDTPS0 R/W-0 SWDTEN(1) bit 0
Unimplemented: Read as `0' WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved SWDTEN: Software Enable or Disable the Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.
bit 0
Note 1:
TABLE 12-8:
Name WDTCON OPTION_REG CONFIG Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Bit 7 -- RAPU CPD Bit 6 -- INTEDG CP Bit 5 -- T0CS MCLRE Bit 4 WDTPS3 T0SE PWRTE Bit 3 WDTPS2 PSA WDTE Bit 2 WSTPS1 PS2 FOSC2 Bit 1 WDTPS0 PS1 FOSC1 Bit 0 SWDTEN PS0 FOSC0 Value on POR, BOR ---0 1000 1111 1111 -- Value on all other Resets ---0 1000 1111 1111 --
Shaded cells are not used by the Watchdog Timer. See Register 12-1 for operation of all Configuration Word register bits.
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12.12 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: * * * * * WDT will be cleared but keeps running. PD bit in the STATUS register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). Other peripherals cannot generate interrupts, since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed.
For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin and the comparators and CVREF should be disabled. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTA should be considered. The MCLR pin must be at a logic high level. Note 1: It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low. 2: The Analog Front-End (AFE) section in the PIC16F639 device is independent of the microcontroller's power-down mode (Sleep). See Section 11.32.2.3 "Sleep Command" for AFE's Sleep mode.
The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. Note: If WUR is enabled (WURE = 0 in Configuration Word), then the Wake-up Reset module will force a device Reset.
12.12.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
12.12.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from RA2/INT pin, PORTA change or a peripheral interrupt.
The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. 6. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. Special event trigger (Timer1 in Asynchronous mode using an external clock). EEPROM write operation completion. Comparator output changes state. Interrupt-on-change. External Interrupt from INT pin.
(c) 2007 Microchip Technology Inc.
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FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 CLKOUT(4) INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Inst(PC) = Sleep Inst(PC - 1) Processor in Sleep Interrupt Latency(3)
PC + 1 Inst(PC + 1) Sleep
PC + 2
PC + 2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy Cycle
Dummy Cycle
XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
12.13 Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP for verification purposes. Note: The entire data EEPROM and Flash program memory will be erased when the code protection is turned off. See the "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information.
12.14 ID Locations
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used.
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12.15 In-Circuit Serial Programming
The PIC12F635/PIC16F636/639 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for: * Power * Ground * Programming Voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RA0 and RA1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204) for more information. RA0 becomes the programming data and RA1 becomes the programming clock. Both RA0 and RA1 are Schmitt Trigger inputs in this mode. After Reset, to place the device into Program/Verify mode, the Program Counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. For complete details of serial programming, please refer to the "PIC12F6XX/16F6XX Memory Programming Specification" (DS41204). A typical In-Circuit Serial Programming connection is shown in Figure 12-11.
12.16 In-Circuit Debugger
Since in-circuit debugging requires the loss of clock, data and MCLR pins, MPLAB(R) ICD 2 development with a 14-pin device is not practical. A special 20-pin PIC16F636 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. Use of the ICD device requires the purchase of a special header. On the top of the header is an MPLAB ICD 2 connector. On the bottom of the header is a 14-pin socket that plugs into the user's target via the 14-pin stand-off connector. When the ICD pin on the PIC16F636 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 12-9 shows which features are consumed by the background debugger:
TABLE 12-9:
Resource I/O pins Stack
DEBUGGER RESOURCES
Description ICDCLK, ICDDATA 1 level Address 0h must be NOP 700h-7FFh
Program Memory
For more information, see the "MPLAB(R) ICD 2 In-Circuit Debugger User's Guide" (DS51331), available on Microchip's web site (www.microchip.com).
FIGURE 12-12:
20-Pin PDIP
20-PIN ICD PINOUT
FIGURE 12-11:
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections
In-Circuit Debug Device
NC ICDMCLR/VPP VDD RA5 RA4 RA3 RC5 RC4 RC3 ICD
1 2 20 19
PIC16F636-ICD
External Connector Signals +5V 0V VPP CLK Data I/O
3 4 5 6 7 8 9 10
18 17 16 15 14 13 12 11
*
PIC16F636 VDD VSS MCLR/VPP/RA3 RA1 RA0
ICDCLK ICDDATA VSS RA0 RA1 RA2 RC0 RC1 RC2 ENPORT
*
*
*
To Normal Connections *Isolation devices (as required).
(c) 2007 Microchip Technology Inc.
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NOTES:
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13.0 INSTRUCTION SET SUMMARY
TABLE 13-1:
Field
f W b k x
The PIC12F635/PIC16F636/639 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 13-1, while the various opcode fields are summarized in Table 13-1. Table 13-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Carry bit Digit carry bit Zero bit Power-down bit
d
PC TO C DC Z PD
FIGURE 13-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 7 k (literal)
0
0
13.1
Read-Modify-Write Operations
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag.
0
k = 11-bit immediate value
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TABLE 13-2:
Mnemonic, Operands
PIC12F635/PIC16F636/639 INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C, DC, Z Z Z Z Z Z Z Z Z
1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2
C C C, DC, Z Z
1, 2 1, 2 1, 2 1, 2 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: f, b f, b f, b f, b k k k - k k k - k - - k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C, DC, Z Z TO, PD Z 1, 2 1, 2 3 3
LITERAL AND CONTROL OPERATIONS 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO, PD C, DC, Z Z
2: 3:
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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13.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a two-cycle instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a two-cycle instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
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MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. 1 1
MOVF FSR, 0
MOVWF Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
Move W to f [ label ] (W) (f) None Move data from W register to register `f'. 1 1 MOVW F OPTION MOVWF f 0 f 127
Words: Cycles: Example:
Before Instruction OPTION = W = After Instruction OPTION = W =
0xFF 0x4F 0x4F 0x4F
After Instruction W= value in FSR register Z=1
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. 1 1
MOVLW 0x5A
NOP Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
No Operation [ label ] None No operation None No operation. 1 1
NOP
MOVLW k
NOP
0 k 255
Words: Cycles: Example:
After Instruction W=
0x5A
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RETFIE Syntax: Operands: Operation: Status Affected: Description: Return from Interrupt [ label ] None TOS PC, 1 GIE None Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE;W contains table
;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table
RETFIE
Words: Cycles: Example:
Words: Cycles: Example:
After Interrupt PC = GIE =
TABLE TOS 1
Before Instruction W = 0x07 After Instruction W = value of k8
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
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RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'.
C Register f
SLEEP Syntax: Operands: Operation:
Enter Sleep mode [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped.
RLF
f,d
Status Affected: Description:
Words: Cycles: Example:
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Before Instruction
After Instruction
REG1 W C
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
C Register f
SUBLW Syntax: Operands: Operation: Description:
Subtract W from literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. C=0 C=1 DC = 0 DC = 1 W>k Wk W<3:0> > k<3:0> W<3:0> k<3:0>
Status Affected: C, DC, Z
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SUBWF Syntax: Operands: Operation: Description: Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f. C=0 C=1 DC = 0 DC = 1 W>f Wf W<3:0> > f<3:0> W<3:0> f<3:0> XORLW Syntax: Operands: Operation: Status Affected: Description: Exclusive OR literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
Status Affected: C, DC, Z
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'.
XORWF Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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NOTES:
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14.0 DEVELOPMENT SUPPORT
14.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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14.2 MPASM Assembler 14.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
14.6 14.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
14.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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14.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 14.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
14.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
14.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC(R) and MCU devices. It debugs and programs PIC(R) and dsPIC(R) Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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14.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
14.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits.
14.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
DS41232D-page 162
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings()
Ambient temperature under bias....................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS/VSST pin .............................................................................................................. 95 mA Maximum current into VDD/VDDT pin ................................................................................................................. 95 mA Input clamp current, IIK (VI < 0 or VI > VDD)............................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO >VDD) ....................................................................................................... 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by PORTA and PORTC (combined) ............................................................................ 95 mA Maximum current sourced PORTA and PORTC (combined) ............................................................................ 95 mA Maximum LC Input Voltage (LCX, LCY, LCZ)(2) loaded, with device ............................................................ 10.0 VPP Maximum LC Input Voltage (LCX, LCY, LCZ)(2) unloaded, without device ................................................. 700.0 VPP Maximum Input Current (rms) into device per LC Channel(2) ........................................................................... 10 mA Human Body ESD rating ........................................................................................................................ 4000 (min.) V Machine Model ESD rating ...................................................................................................................... 400 (min.) V Note 1: Power dissipation for PIC12F635/PIC16F636/639 (AFE section not included) is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL). Power dissipation for AFE section is calculated as follows: PDIS = VDD x IACT = 3.6V x 16 A = 57.6 W Specification applies to the PIC16F639 only.
2:
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a `low' level to the MCLR pin, rather than pulling this pin directly to VSS.
(c) 2007 Microchip Technology Inc.
DS41232D-page 163
PIC12F635/PIC16F636/639
FIGURE 15-1: PIC12F635/16F636 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
5.5 5.0 4.5 VDD (V) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 Frequency (MHz) Note 1: 2: The shaded region indicates the permissible combinations of voltage and frequency. Cross-hatched area is for HFINTOSC and EC modes only. 20
FIGURE 15-2:
PIC16F639 VOLTAGE-FREQUENCY GRAPH, -40C TA +85C
5.5 5.0 4.5
VDD (V)
4.0 3.6 3.0 2.5 2.0 0 4 8 10 Frequency (MHz) 20
Note 1: 2:
The shaded region indicates the permissible combinations of voltage and frequency. Cross-hatched area is for HFINTOSC and EC modes only.
DS41232D-page 164
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 15-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125 5% 85 Temperature (C)
60
2%
25
1%
0
-40 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
DS41232D-page 165
PIC12F635/PIC16F636/639
15.1 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No. D001 D001A D001B D001C D002 D003 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal
Sym VDD
Characteristic Supply Voltage
2.0 2.0 3.0 4.5 1.5* --
-- -- -- -- -- VSS
5.5 5.5 5.5 5.5 -- --
V V V V V V
FOSC < = 4 MHz FOSC < = 8 MHz, HFINTOSC, EC FOSC < = 10 MHz FOSC < = 20 MHz Device in Sleep mode See Section 12.3 "Power-on Reset" for details.
D004
SVDD
VDD Rise Rate to ensure 0.05* internal Power-on Reset signal Brown-out Reset 2.0
--
--
V/ms See Section 12.3 "Power-on Reset" for details. V
D005
VBOD
2.1
2.2
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
DS41232D-page 166
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Sym IDD Device Characteristics Supply Current(1,2) Min -- -- -- D011 -- -- -- D012 -- -- -- D013 -- -- -- D014 -- -- -- D015 -- -- -- D016 -- -- -- D017 -- -- -- D018 -- -- -- D019 -- -- Typ 11 18 35 140 220 380 260 420 0.8 130 215 360 220 375 0.65 8 16 31 340 500 0.8 410 700 1.30 230 400 0.63 2.6 2.6 Max 16 28 54 240 380 550 360 650 1.1 220 360 520 340 550 1.0 20 40 65 450 700 1.2 650 950 1.65 400 680 1.1 3.25 3.25 Units VDD A A A A A A A A mA A A A A A mA A A A A A mA A A mA A A mA mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode FOSC = 8 MHz HFINTOSC mode FOSC = 4 MHz HFINTOSC mode FOSC = 31 kHz LFINTOSC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32.768 kHz LP Oscillator mode
DC CHARACTERISTICS Param No. D010
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. MCU only, Analog Front-End not included. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. MCU only, Analog Front-End not included. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
(c) 2007 Microchip Technology Inc.
DS41232D-page 167
PIC12F635/PIC16F636/639
15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Sym IPD Device Characteristics Power-down Base Current(4) Min -- -- -- D021 -- -- -- D022A D022B -- -- -- -- -- D023 -- -- -- D024A -- -- -- D024B -- -- -- D025 -- -- -- Typ 0.15 0.20 0.35 1.0 2.0 3.0 58 109 22 25 33 32 60 120 30 45 75 39 59 98 4.5 5.0 6.0 Max 1.2 1.5 1.8 2.2 4.0 7.0 60 122 28 35 45 45 78 160 36 55 95 47 72 124 7.0 8.0 12 Units VDD A A A A A A A A A A A A A A A A A A A A A A A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 T1OSC Current(3) CVREF Current(1) (low-range) CVREF Current(1) (high-range) Comparator Current(3) PLVD Current BOR Current(1) Note WDT, BOR, Comparators, VREF and T1OSC disabled WDT Current(1) DC CHARACTERISTICS Param No. D020
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. MCU only, Analog Front-End not included. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. MCU only, Analog Front-End not included. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS41232D-page 168
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.3 DC Characteristics: PIC12F635/PIC16F636-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Sym IDD Device Characteristics Supply Current(1,2) Min -- -- -- D011E -- -- -- D012E -- -- -- D013E -- -- -- D014E -- -- -- D015E -- -- -- D016E -- -- -- D017E -- -- -- D018E -- -- -- D019E -- -- Typ 11 18 35 Max 16 28 54 Units VDD A A A A A A A A mA A A A A A mA A A A A A mA A A mA A A mA mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode FOSC = 4 MHz HFINTOSC mode FOSC = 31 kHz LFINTOSC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32.768 kHz LP Oscillator mode
DC CHARACTERISTICS Param No. D010E
140 220 380 260 420 0.8 130 215 360 220 375 0.65 8 16 31 340 500 0.8 410 700 1.30 230 400 0.63 2.6 2.8
240 380 550 360 650 1.1 220 360 520 340 550 1.0 20 40 65 450 700 1.2 650 950 1.65 100 680 1.1 3.25 3.35
FOSC = 8 MHz HFINTOSC mode
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
(c) 2007 Microchip Technology Inc.
DS41232D-page 169
PIC12F635/PIC16F636/639
15.3 DC Characteristics: PIC12F635/PIC16F636-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Sym IPD Device Characteristics Power-down Base Current(4) Min -- -- -- D021 -- -- -- D022A D022B -- -- -- -- -- D023 -- -- -- D024A -- -- -- D024B -- -- -- D025 -- -- -- Typ 0.15 0.20 0.35 1.0 2.0 3.0 42 85 22 25 33 32.3 60 120 30 45 75 39 59 98 4.5 5.0 6.0 Max 1.2 1.5 1.8 17.5 19 22 60 122 48 55 65 45 78 160 36 55 95 47 72 124 25 30 40 Units VDD A A A A A A A A A A A A A A A A A A A A A A A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 T1OSC Current(3) CVREF Current(1) (low-range) CVREF Current(1) (high-range) Comparator Current(1) PLVD Current BOR Current(1) WDT Current(1) Note WDT, BOR, Comparators, VREF and T1OSC disabled DC CHARACTERISTICS Param No. D020
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS41232D-page 170
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.4 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Sym VIL
Characteristic Input Low Voltage I/O ports: with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (RC mode) OSC1 (XT and LP modes)(1) OSC1 (HS mode)
(1)
D030 D030A D031 D032 D033 D033A VIH D040 D040A D041 D042 D043 D043A D043B IIL D060 D060A D060B D061 D063 D070 D071 IPUR IPDR VOL D080 D083
VSS VSS VSS VSS VSS VSS
-- -- -- -- -- --
0.8 0.15 VDD 0.2 VDD 0.2 VDD 0.3 0.3 VDD
V V V V V V
4.5V VDD 5.5V Otherwise Entire range
Input High Voltage I/O ports: with TTL buffer 2.0 (0.25 VDD + 0.8) 0.8 VDD 0.8 VDD 1.6 0.7 VDD 0.9 VDD -- -- -- -- -- 50 50 -- -- -- -- -- -- -- 0.1 0.1 0.1 0.1 0.1 250 250 VDD VDD VDD VDD VDD VDD VDD 1 1 1 5 5 400 400 V V V V V V V A A A A A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD, XT, HS and LP oscillator configuration VDD = 5.0V, VPIN = VSS VDD = 5.0V, VPIN = VDD (Note 1) (Note 1) 4.5V VDD 5.5V Otherwise Entire range
with Schmitt Trigger buffer MCLR OSC1 (XT and LP modes) OSC1 (HS mode) OSC1 (RC mode) Input Leakage Current(2) I/O ports Analog inputs VREF MCLR(3) OSC1 PORTA Weak Pull-up Current PORTA Weak Pull-down Current Output Low Voltage I/O ports OSC2/CLKOUT (RC mode)
-- --
-- --
0.6 0.6
V V
IOL = 8.5 mA, VDD = 4.5V (Ind.) IOL = 1.6 mA, VDD = 4.5V (Ind.) IOL = 1.2 mA, VDD = 4.5V (Ext.)
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 9.4.1 "Using the Data EEPROM" for additional information.
(c) 2007 Microchip Technology Inc.
DS41232D-page 171
PIC12F635/PIC16F636/639
15.4 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Sym VOH
Characteristic Output High Voltage I/O ports OSC2/CLKOUT (RC mode)
D090 D092 D100 IULP
VDD - 0.7 VDD - 0.7 --
-- -- 200
-- -- --
V V nA
IOH = -3.0 mA, VDD = 4.5V (Ind.) IOH = -1.3 mA, VDD = 4.5V (Ind.) IOH = -1.0 mA, VDD = 4.5V (Ext.)
Ultra Low-power Wake-up Current Capacitive Loading Specs on Output Pins
D101
COSC2 OSC2 pin
--
--
15*
pF
In XT, HS and LP modes when external clock is used to drive OSC1
D101A CIO D120 D121 ED VDRW
All I/O pins Data EEPROM Memory Byte Endurance Byte Endurance VDD for Read/Write
-- 100K 10K VMIN
-- 1M 100K --
50* -- -- 5.5
pF E/W E/W V -40C TA +85C +85C TA +125C Using EECON1 to read/write VMIN = Minimum operating voltage
D120A ED
D122 D123 D124
TDEW TRETD TREF
Erase/Write cycle time Characteristic Retention Number of Total Erase/Write Cycles before Refresh(4) Program Flash Memory Cell Endurance Cell Endurance VDD for Read VDD for Erase/Write Erase/Write cycle time Characteristic Retention
-- 40 1M
5 -- 10M
6 -- --
ms Year Provided no other specifications are violated E/W -40C TA +85C
D130 D131 D132 D133 D134
EP VPR VPEW TPEW TRETD
10K 1K VMIN 4.5 -- 40
100K 10K -- -- 2 --
-- -- 5.5 5.5 2.5 --
E/W E/W V V ms
-40C TA +85C +85C TA +125C VMIN = Minimum operating voltage
D130A ED
Year Provided no other specifications are violated
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 9.4.1 "Using the Data EEPROM" for additional information.
DS41232D-page 172
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.5 DC Characteristics: PIC16F639-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min 2.0 2.0 1.5* -- Typ Max Units -- -- -- VSS 3.6 3.6 -- -- V V V V Conditions FOSC 10 MHz Analog Front-End VDD voltage. Treated as VDD in this document. Device in Sleep mode See Section 12.3 "Power-on Reset" for details. Analog Front-End POR voltage. DC CHARACTERISTICS Param No. D001 D001A D002 D003 Sym VDD VDDT VDR VPOR Characteristic Supply Voltage Supply Voltage (AFE) RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Start Voltage (AFE) to ensure internal Poweron Reset signal
D003A
VPORT
--
--
1.8
V
D004
SVDD
VDD Rise Rate to ensure 0.05* internal Power-on Reset signal Brown-out Reset Turn-on Resistance or Modulation Transistor Digital Input Pull-Up Resistor CS, SCLK Analog Input Leakage Current LCX, LCY, LCZ LCCOM 2.0 -- 50
--
--
V/ms See Section 12.3 "Power-on Reset" for details. V Ohm VDD = 3.0V
D005 D006 D007
VBOD RM RPU
2.1 50 200
2.2 100 350
kOhm VDD = 3.6V
D008
IAIL
-- --
-- --
1 1
A A
VDD = 3.6V, VSS VIN VDD, tested at Sleep mode
*
These parameters are characterized but not tested.
Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
(c) 2007 Microchip Technology Inc.
DS41232D-page 173
PIC12F635/PIC16F636/639
15.6 DC Characteristics: PIC16F639-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Supply Voltage 2.0V VDD 3.6V Conditions Sym Device Characteristics
(1,2,3)
DC CHARACTERISTICS
Param No. D010
Min
Typ
Max
Units VDD Note FOSC = 32.768 kHz LP Oscillator mode FOSC = 1 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz EC Oscillator mode FOSC = 31 kHz LFINTOSC mode FOSC = 4 MHz HFINTOSC mode FOSC = 4 MHz EXTRC mode WDT, BOR, Comparators, VREF and T1OSC disabled (excludes AFE) WDT Current(1) BOR Current(1) PLVD Current Comparator Current(1) CVREF Current(1) (high-range) CVREF Current(1) (low-range) T1OSC Current(1) A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
IDD
Supply Current
-- --
11 18 140 220 260 420 130 215 220 375 8 16 340 500 230 400 0.15 0.20 1.2 2.0 42 22 25 32 60 30 45 39 59 4.5 5.0
16 28 240 380 360 650 220 360 340 550 20 40 450 700 400 680 1.2 1.5 2.2 4.0 60 28 35 45 78 36 55 47 72 7.0 8.0
2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0
D011
-- --
D012
-- --
D013
-- --
D014
-- --
D015
-- --
D016
-- --
D017 Power-down Base Current(4)
-- --
D020
IPD
-- --
D021
IWDT
-- --
D022A D022B
IBOR ILVD
-- -- --
D023
ICMP
-- --
D024A
IVREFHS
-- --
D024B
IVREFLS
-- --
D025
IT1OSC
-- --
D026
IACT
Active Current of AFE only (receiving signal) 1 LC Input Channel Signal 3 LC Input Channel Signals Standby Current of AFE only (not receiving signal) 1 LC Input Channel Enabled 2 LC Input Channels Enabled 3 LC Input Channels Enabled Sleep Current of AFE only
-- --
10 13
-- 18
A A
3.6 3.6
CS = VDD; Input = Continuous Wave (CW); Amplitude = 300 mVPP. All channels enabled. CS = VDD; ALERT = VDD
D027
ISTDBY
-- -- -- --
3 4 5 0.2
5 6 7 1
A A A
3.6 3.6 3.6 3.6 CS = VDD; ALERT = VDD
D028 Note 1: 2:
ISLEEP
3:
4:
Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. MCU only, Analog Front-End not included. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. MCU only, Analog Front-End not included. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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15.7 DC Characteristics: PIC16F639-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Supply Voltage 2.0V VDD 3.6V Characteristic Input Low Voltage I/O ports: D030A D031 D032 D033 D033A D034 VIH with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (RC mode) OSC1 (XT and LP modes)(1) OSC1 (HS mode)(1) Digital Input Low Voltage Input High Voltage I/O ports: D040 D040A D041 D042 D043 D043A D043B with Schmitt Trigger buffer MCLR OSC1 (XT and LP modes) OSC1 (HS mode) OSC1 (RC mode) Digital Input High Voltage D044 IIL D060 D060A D060B D061 D063 SCLK, CS, SDIO for Analog Front-End (AFE) Input Leakage Current(2) I/O ports Analog inputs VREF MCLR(3) OSC1 Digital Input Leakage Current(2) D064 D064A D070 D071 IPUR IPDR VOL D080 D083 SDI for Analog Front-End (AFE) SCLK, CS for Analog Front-End (AFE) PORTA Weak Pull-up Current PORTA Weak Pull-down Current Output Low Voltage I/O ports OSC2/CLKOUT (RC mode) Digital Output Low Voltage D084 * 1: 2: 3: 4: ALERT, LFDATA/SDIO for Analog Front-End (AFE) -- -- VSS + 0.4 V -- -- -- -- 0.6 0.6 V V IOL = 8.5 mA, VDD = 3.6V (Ind.) IOL = 1.6 mA, VDD = 3.6V (Ind.) IOL = 1.2 mA, VDD = 3.6V (Ext.) Analog Front-End section IOL = 1.0 mA, VDD = 2.0V -- -- 50* 50 -- -- 250 250 1 1 400 400 A A A A -- -- -- -- -- 0.1 0.1 0.1 0.1 0.1 1 1 1 5 5 A A A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD, XT, HS and LP oscillator configuration VDD = 3.6V, Analog Front-End section VSS VPIN VDD VPIN VDD VDD = 3.6V, VPIN = VSS VDD = 3.6V, VPIN = VDD 0.8 VDD -- VDD V with TTL buffer (0.25 VDD + 0.8) 0.8 VDD 0.8 VDD 1.6 0.7 VDD 0.9 VDD -- -- -- -- -- -- VDD VDD VDD VDD VDD VDD V V V V V V Analog Front-End section (Note 1) (Note 1) VSS VSS VSS VSS VSS VSS -- -- -- -- -- -- 0.15 VDD 0.2 VDD 0.2 VDD 0.3 0.3 VDD 0.3 VDD V V V V V V Analog Front-End section Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Sym VIL
Note
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. See Section 9.4.1 "Using the Data EEPROM" for additional information
(c) 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639
15.7 DC Characteristics: PIC16F639-I (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Supply Voltage 2.0V VDD 3.6V Characteristic Output High Voltage I/O ports OSC2/CLKOUT (RC mode) Digital Output High Voltage D093 LFDATA/SDIO for Analog Front-End (AFE) Capacitive Loading Specs on Output Pins D100 D101 D102 COSC2 CIO IULP OSC2 pin All I/O pins Ultra Low-power Wake-up Current Data EEPROM Memory D120 D120A D121 D122 D123 D124 ED ED VDRW TDEW TRETD TREF Byte Endurance Byte Endurance VDD for Read/Write Erase/Write cycle time Characteristic Retention Number of Total Erase/Write Cycles before Refresh(1) Program Flash Memory D130 D130A D131 D132 D133 D134 EP ED VPR VPEW TPEW TRETD * 1: 2: 3: 4: Cell Endurance Cell Endurance VDD for Read VDD for Erase/Write Erase/Write cycle time Characteristic Retention 10K 1K VMIN 4.5 -- 40 100K 10K -- -- 2 -- -- -- 5.5 5.5 2.5 -- E/W E/W V V ms Year Provided no other specifications are violated -40C TA +85C +85C TA +125C VMIN = Minimum operating voltage 100K 10K VMIN -- 40 1M 1M 100K -- 5 -- 10M -- -- 5.5 6 -- -- E/W E/W V ms Year E/W Provided no other specifications are violated -40C TA +85C -40C TA +85C +85C TA +125C Using EECON1 to read/write VMIN = Minimum operating voltage -- -- -- -- -- 200 15* 50* -- pF pF nA In XT, HS and LP modes when external clock is used to drive OSC1 VDD - 0.5 -- -- V VDD - 0.7 VDD - 0.7 -- -- -- -- V V IOH = -3.0 mA, VDD = 3.6V (Ind.) IOH = -1.3 mA, VDD = 3.6V (Ind.) IOH = -1.0 mA, VDD = 3.6V (Ext.) Analog Front-End (AFE) section IOH = -400 A, VDD = 2.0V Min Typ Max Units Conditions DC CHARACTERISTICS Param No.
Sym VOH
D090 D092
Note
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. See Section 9.4.1 "Using the Data EEPROM" for additional information
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15.8 Thermal Considerations
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Para m No. Sym Characteristic Thermal Resistance Junction to Ambient Typ 84.6 163.0 52.4 52.4 69.8 85.0 100.4 46.3 108.1 41.2 38.8 3.0 3.0 32.5 31.0 31.7 2.6 32.2 150 -- -- Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C W W Conditions
TH01 JA
TH02
TH03 TH04 TH05 TH06 TH07 Note
8-pin PDIP package 8-pin SOIC package PIC12F635 8-pin DFN 4x4x0.9 mm package 8-pin DFN-S 6x5 mm package 14-pin PDIP package 14-pin SOIC package PIC16F636 14-pin TSSOP package 16-pin QFN 4x0.9mm package PIC16F639 20-pin SSOP package JC Thermal Resistance 8-pin PDIP package Junction to Case 8-pin SOIC package PIC12F635 8-pin DFN 4x4x0.9 mm package 8-pin DFN-S 6x5 mm package 14-pin PDIP package 14-pin SOIC package PIC16F636 14-pin TSSOP package 16-pin QFN 4x0.9mm package PIC16F639 20-pin SSOP package TJ Junction Temperature For derated power calculations PD Power Dissipation PD = PINTERNAL + PI/O PINTERNAL Internal Power Dissipation PINTERNAL = IDD x VDD (NOTE 1) PI/O I/O Power Dissipation -- W PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) PDER Derated Power -- W PDER = (TJ - TA)/JA (NOTE 2, 3) 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature. 3: Maximum allowable power dissipation is the lower value of either the absolute maximum total power dissipation or derated power (PDER).
(c) 2007 Microchip Technology Inc.
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15.9 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCLK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid High-impedance
FIGURE 15-4:
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins 15 pF for OSC2 output
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15.10 AC Characteristics: PIC12F635/PIC16F636/639 (Industrial, Extended)
FIGURE 15-5: CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1/CLKIN OS02 OS04 OS03 OSC2/CLKOUT (LP, XT, HS Modes) OS04
OSC2/CLKOUT (CLKOUT Mode)
TABLE 15-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. OS01 Sym FOSC Characteristic External CLKIN Frequency(1) Min DC DC DC DC -- 0.1 1 DC 27 250 50 50 -- 250 50 250 Typ -- -- -- -- 32.768 -- -- -- -- -- -- -- 30.5 -- -- -- Max 37 4 20 20 -- 4 20 4 -- 10,000 1,000 -- Units kHz MHz MHz MHz kHz MHz MHz MHz s ns ns ns s ns ns ns Conditions LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode RC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode RC Oscillator mode
Oscillator Frequency(1)
OS02
TOSC
External CLKIN Period(1)
Oscillator Period(1)
200 TCY DC ns TCY = 4/FOSC 2 -- -- s LP oscillator 100 -- -- ns XT oscillator 20 -- -- ns HS oscillator OS05* TosR, External CLKIN Rise, 0 -- 50 ns LP oscillator TosF External CLKIN Fall 0 -- 25 ns XT oscillator 0 -- 15 ns HS oscillator * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.
OS03 OS04*
TCY TosH, TosL
Instruction Cycle Time(1) External CLKIN High, External CLKIN Low
(c) 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639
TABLE 15-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS06 OS07 OS08 Sym TWARM TSC HFOSC Characteristic Internal Oscillator Switch when running(3) Fail-Safe Sample Clock Period(1) Internal Calibrated HFINTOSC Frequency(2) Freq Tolerance -- -- 1% 2% 5% Min -- -- 7.92 7.84 7.60 Typ -- 21 8.0 8.0 8.0 Max 2 -- 8.08 8.16 8.40 Units TOSC ms MHz MHz MHz Conditions Slowest clock LFINTOSC/64 VDD = 3.5V, 25C 2.5V VDD 5.5V, 0C TA +85C 2.0V VDD 5.5V, -40C TA +85C (Ind.), -40C TA +125C (Ext.)
OS09* OS10*
LFOSC
Internal Uncalibrated LFINTOSC Frequency
-- -- -- --
15 5.5 3.5 3
31 12 7 6
45 24 14 11
kHz s s s VDD = 2.0V, -40C to +85C VDD = 3.0V, -40C to +85C VDD = 5.0V, -40C to +85C
TIOSCST HFINTOSC Oscillator Wake-up from Sleep Start-up Time
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: By design.
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FIGURE 15-6:
Cycle
CLKOUT AND I/O TIMING
Write Q4 Fetch Q1 Read Q2 Execute Q3
FOSC OS11 CLKOUT OS19 OS13 I/O pin (Input) OS15 I/O pin (Output) Old Value OS18, OS19 OS14 New Value OS17 OS20 OS21 OS16 OS18 OS12
TABLE 15-3:
CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS11 OS12 OS13 OS14 OS15* OS16 OS17 OS18 OS19 OS20* OS21* * Note 1: 2: Sym TOSH2CKL TOSH2CKH TCKL2IOV TIOV2CKH TOSH2IOV TOSH2IOI TIOV2OSH TIOR TIOF TINP TRAP Characteristic FOSC to CLKOUT (1) FOSC to CLKOUT
(1)
Min -- -- -- TOSC + 200 ns -- 50 20 -- -- -- -- 25 TCY
Typ -- -- -- -- 50 -- -- 40 15 28 15 -- --
Max 70 72 20 -- 70 -- -- 72 32 55 30 -- --
Units ns ns ns ns ns ns ns ns ns ns ns
Conditions VDD = 5.0V VDD = 5.0V
CLKOUT to Port out Port input valid before
valid(1) CLKOUT(1)
FOSC (Q1 cycle) to Port out valid FOSC (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to FOSC (Q2 cycle) (I/O in setup time) Port output rise time(2) Port output fall time(2) INT pin input high or low time PORTA interrupt-on-change new input level time
VDD = 5.0V VDD = 5.0V
VDD = 2.0V VDD = 5.0V VDD = 2.0V VDD = 5.0V
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. Includes OSC2 in CLKOUT mode.
(c) 2007 Microchip Technology Inc.
DS41232D-page 181
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FIGURE 15-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Start-Up Time 32 30
Internal Reset(1) Watchdog Timer Reset(1) 34 I/O pins Note 1: Asserted low. 31 34
FIGURE 15-8:
VDD
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VBOR
VBOR + VHYST
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset (due to BOR) *
33*
64 ms delay only if PWRTE bit in the Configuration Word register is programmed to `0'.
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TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 30 31 32 33* 34* Sym TMCL TWDT TOST TPWRT TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period(1, 2) Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Voltage Brown-out Reset Hysteresis Brown-out Reset Minimum Detection Period Min 2 5 10 10 -- 40 -- Typ -- -- 16 16 1024 65 -- Max -- -- 29 31 -- 140 2.0 Units s s ms ms Conditions VDD = 5V, -40C to +85C VDD = 5V VDD = 5V, -40C to +85C VDD = 5V
TOSC (NOTE 3) ms s
35 36* 37*
VBOR VHYST TBOR
2.0 -- 100
-- 50 --
2.2 -- --
V mV s
(NOTE 4) VDD VBOR
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
(c) 2007 Microchip Technology Inc.
DS41232D-page 183
PIC12F635/PIC16F636/639
FIGURE 15-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 41
42
T1CKI 45 47 46 49
TMR0 or TMR1
TABLE 15-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 40* 41* 42* Sym TT0H TT0L TT0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 -- 2 TOSC Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions
45*
TT1H
T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler Asynchronous T1CKI Low Time Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous
-- -- -- -- -- -- --
-- -- -- -- -- -- --
ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46*
TT1L
47*
TT1P
T1CKI Input Synchronous Period Asynchronous
-- 32.768 --
-- -- 7 TOSC
ns kHz -- Timers in Sync mode
48 49*
FT1
Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN)
TCKEZTMR1 Delay from External Clock Edge to Timer Increment *
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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TABLE 15-6: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. CM01 CM02 Sym VOS VCM Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time Comparator Mode Change to Output Valid Falling Rising CM05* TMC2COV Min -- 0 +55 -- -- -- Typ 5.0 -- -- 150 200 -- Max 10 VDD - 1.5 -- 600 1000 10 Units mV V dB ns ns s (NOTE 1) Comments (VDD - 1.5)/2
CM03* CMRR CM04* TRT
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV.
TABLE 15-7:
COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. CV01* CV02* CV03* CV04* Sym CLSB CACC CR CST Characteristics Step Size(2) Absolute Accuracy Unit Resistor Value (R) Settling Time(1) Min -- -- -- -- -- -- Typ VDD/24 VDD/32 -- -- 2k -- Max -- -- 1/2 1/2 -- 10 Units V V LSb LSb s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from `0000' to `1111'. 2: See Section 7.11 "Comparator Voltage Reference" for more information.
TABLE 15-8:
PIC12F635/PIC16F636 PLVD CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Operating Voltage VDD Range 2.0V-5.5V Min 1.900 2.000 2.100 2.200 3.825 4.025 4.325 -- Typ 2.0 2.1 2.2 2.3 4.0 4.2 4.5 50 25 Max 2.125 2.225 2.325 2.425 4.200 4.400 4.700 -- Units V V V V V V V s VDD = 5.0V VDD = 3.0V Conditions
DC CHARACTERISTICS Sym. VPLVD PLVD Voltage Characteristic LVDL<2:0> = 001 LVDL<2:0> = 010 LVDL<2:0> = 011 LVDL<2:0> = 100 LVDL<2:0> = 101 LVDL<2:0> = 110 LVDL<2:0> = 111 *TPLVDS PLVD Settling time
* These parameters are characterized but not tested Data in `Typ' column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC12F635/PIC16F636/639
TABLE 15-9: PIC16F639 PLVD CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +85C Operating Voltage VDD Range 2.0V-5.5V Min 1.900 2.000 2.100 2.200 3.825 4.025 4.325 -- Typ 2.0 2.1 2.2 2.3 4.0 4.2 4.5 50 25 Max 2.100 2.200 2.300 2.400 4.175 4.375 4.675 -- Units V V V V V V V s VDD = 5.0V VDD = 3.0V Conditions DC CHARACTERISTICS Sym. VPLVD PLVD Voltage Characteristic LVDL<2:0> = 001 LVDL<2:0> = 010 LVDL<2:0> = 011 LVDL<2:0> = 100 LVDL<2:0> = 101 LVDL<2:0> = 110 LVDL<2:0> = 111 *TPLVDS PLVD Settling time
* These parameters are characterized but not tested Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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15.11 AC Characteristics: Analog Front-End for PIC16F639 (Industrial)
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V VDD 3.6V Operating temperature -40C TAMB +85C for industrial LC Signal Input Sinusoidal 300 mVPP Carrier Frequency 125 kHz LCCOM connected to VSS Characteristic LC Input Sensitivity 1 3.0 6 mVPP Min Typ Max Units Conditions VDD = 3.0V Output enable filter disabled AGCSIG = 0; MODMIN = 00 (33% modulation depth setting) Input = Continuous Wave (CW) Output = Logic level transition from low-tohigh at sensitivity level for CW input. VDD = 3.0V, Force IIN = 5 A VDD = 2.0V, VIN = 8 VDC VDD = 3.0V No sensitivity reduction selected Max reduction selected Monotonic increment in attenuation value from setting = 0000 to 1111 by design VDD = 3.0V 63 38 13 0 -- 44 75 50 25 12 0 63 87 62 37 24 -- 82 % % % % pF pF VDD = 3.0V, Config. Reg. 1, bits <6:1> Setting = 000000 63 pF +/- 30% Config. Reg. 1, bits <6:1> Setting = 111111 63 steps, 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design VDD = 3.0V, Config. Reg. 2, bits <6:1> Setting = 000000 63 pF +/- 30% Config. Reg. 2, bits <6:1> Setting = 111111 63 steps, 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design VDD = 3.0V, Config. Reg. 3, bits<6:1> Setting = 000000 63 pF +/- 30% Config. Reg. 3, bits<6:1> Setting = 111111 63 steps, 1 pF/step Monotonic increment in capacitor value from setting = 000000 to 111111 by design Characterized at bench. Input data rate, characterized at bench. Characterized at bench test VDD = 3.0V MOD depth setting = 50% Input conditions: Amplitude = 300 mVPP Modulation depth = 80% VDD = 3.0V MOD depth setting = 50% Input conditions: Amplitude = 300 mVPP Modulation depth = 80%
Param No. AF01
Sym. VSENSE
AF02 AF03 AF04
VDE_Q RFLM SADJ
Coil de-Q'ing Voltage RF Limiter (RFLM) must be active RF Limiter Turn-on Resistance (LCX, LCY, LCZ) Sensitivity Reduction
3 --
-- 300
5 700
V Ohm
-- --
0 -30
-- --
dB dB
AF05
VIN_MOD
Minimum Modulation Depth 75% 12% 50% 12% 25% 12% 12% 12% LCX Tuning Capacitor
AF06
CTUNX
AF07
CTUNY
LCY Tuning Capacitor -- 44 0 63 -- 82 pF pF
AF08
CTUNZ
LCZ Tuning Capacitor -- 44 0 63 -- 82 pF pF
AF09 AF10 AF11 AF12
FCARRIER Carrier frequency FMOD C_Q TDR Input modulation frequency Q of Trimming Capacitors Demodulator Charge Time (delay time of demodulated output to rise)
-- -- 50* --
125 -- -- 50
-- 10 -- --
kHz kHz pF s
AF13
TDF
Demodulator Discharge Time (delay time of demodulated output to fall)
--
50
--
s
* Note 1: 2:
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF). Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
(c) 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639
15.11 AC Characteristics: Analog Front-End for PIC16F639 (Industrial) (Continued)
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V VDD 3.6V Operating temperature -40C TAMB +85C for industrial LC Signal Input Sinusoidal 300 mVPP Carrier Frequency 125 kHz LCCOM connected to VSS Characteristic Min -- Typ 0.5 Max -- Units s Conditions VDD = 3.0V Time is measured from 10% to 90% of amplitude VDD = 3.0V Time is measured from 10% to 90% of amplitude Time required for AGC stabilization Equivalent to two Internal clock cycle (FOSC) AGC stabilization time
Param No. AF14
Sym.
TLFDATAR Rise time of LFDATA
AF15
TLFDATAF Fall time of LFDATA
--
0.5
--
s
AF16 AF17 AF18
TAGC TPAGC TSTAB
AGC initialization time High time after AGC settling time AGC stabilization time plus high time (after AGC settling time) (TAGC + TPAGC) Gap time after AGC settling time Time from exiting Sleep or POR to being ready to receive signal Minimum time AGC level must be held after receiving AGC Preserve command Internal RC oscillator frequency (10%) Inactivity timer time-out Alarm timer time-out LC Pin Input Impedance LCX, LCY, LCZ LC Pin Input Capacitance LCX, LCY, LCZ Time element of pulse Minimum output enable filter high time OEH (Bits Config0<7:6>) 01 = 1 ms 10 = 2 ms 11 = 4 ms 00 = Filter Disabled Minimum output enable filter low time OEL (Bits Config0<5:4>) 00 = 1 ms 01 = 1 ms 10 = 2 ms 11 = 4 ms
-- -- 4
3.5* 62.5 --
-- -- --
ms s ms
AF19 AF20 AF21
TGAP TRDY TPRES
200 -- 5*
-- -- --
-- 50* --
s ms ms
Typically 1 TE
AGC level must not change more than 10% during TPRES. Internal clock trimmed at 32 kHz during test 512 cycles of RC oscillator @ FOSC 1024 cycles of RC oscillator @ FOSC
AF22 AF23 AF24 AF25 AF26 AF27 AF28
FOSC TINACT TALARM RLC CIN TE TOEH
28.8 14.4 28.8 -- -- 100
32 16 32 1* 24 --
35.2 17.6 35.2 -- -- --
kHz ms ms
MOhm Device in Standby mode pF s RC oscillator = FOSC Viewed from the pin input: (Note 1) LCCOM grounded. Vdd = 3.0V, FCARRIER = 125 kHz
32 (~1ms) 64 (~2ms) 128 (~4ms) --
-- -- -- --
-- -- -- --
clock count
AF29
TOEL
32 (~1ms) 32 (~1ms) 64 (~2ms) 128 (~4ms)
-- -- -- --
-- -- -- --
clock count
RC oscillator = FOSC Viewed from the pin input: (Note 2)
* Note 1: 2:
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF). Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
DS41232D-page 188
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.11 AC Characteristics: Analog Front-End for PIC16F639 (Industrial) (Continued)
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V VDD 3.6V Operating temperature -40C TAMB +85C for industrial LC Signal Input Sinusoidal 300 mVPP Carrier Frequency 125 kHz LCCOM connected to VSS Characteristic Maximum output enable filter period OEH 01 01 01 01 10 10 10 10 11 11 11 11 00 AF31 IRSSI OEL 00 = 01 = 10 = 11 = 00 01 10 11 00 01 10 11 XX = = = = = = = = TOEH TOEL 1 ms 1 ms (filter 1) 1 ms 1 ms (filter 1) 1 ms 2 ms (filter 2) 1 ms 4 ms (filter 3) 2 ms 2 ms 2 ms 2 ms 4 ms 4 ms 4 ms 4 ms 1 ms (filter 4) 1 ms (filter 4) 2 ms (filter 5) 4 ms (filter 6) 1 ms (filter 7) 1 ms (filter 7) 2 ms (filter 8) 4 ms (filter 9) Min Typ Max Units Conditions RC oscillator = FOSC
Param No. AF30
Sym. TOET
-- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- 100
96 (~3ms) 96 (~3ms) 128 (~4ms) 192 (~6ms) 128 (~4ms) 128 (~4ms) 160 (~5ms) 250 (~8ms) 192 (~6ms) 192 (~6ms) 256 (~8ms) 320 (~10ms) -- --
clock count
= Filter Disabled
LFDATA output appears as long as input signal level is greater than VSENSE. A VDD = 3.0V, VIN = 0 to 4 VPP Linearly increases with input signal amplitude. Tested at VIN = 40 mVPP, 400 mVPP, and 4 VPP VIN = 40 mVPP VIN = 400 mVPP VIN = 4 VPP Tested at room temperature only
RSSI current output
-- -- -- AF32 * Note 1: 2: IRSSILR RSSI current linearity -15
1 10 100 --
-- -- -- 15
A A A %
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF). Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
(c) 2007 Microchip Technology Inc.
DS41232D-page 189
PIC12F635/PIC16F636/639
15.12 SPI Timing: Analog Front-End (AFE) for PIC16F639
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V VDD 3.6V Operating temperature -40C TAMB +85C for industrial LC Signal Input Sinusoidal 300 mVPP Carrier Frequency 125 kHz LCCOM connected to VSS Characteristic SCLK Frequency CS fall to first SCLK edge setup time SDI setup time SDI hold time SCLK high time SCLK low time SDO setup time SCLK last edge to CS rise setup time CS high time CS rise to SCLK edge setup time SCLK edge to CS fall setup time Rise time of SPI data (SPI Read command) Fall time of SPI data (SPI Read command) Min -- 100 30 50 150 150 -- 100 500 50 50 -- -- Typ -- -- -- -- -- -- -- -- -- -- -- 10 10 Max 3 -- -- -- -- -- 150 -- -- -- -- -- -- Units MHz ns ns ns ns ns ns ns ns ns ns ns ns SCLK edge when CS is high VDD = 3.0V. Time is measured from 10% to 90% of amplitude VDD = 3.0V. Time is measured from 90% to 10% of amplitude Conditions
Param
AF33 AF34 AF35 AF36 AF37 AF38 AF39 AF40 AF41 AF42 AF43 AF44 AF45
Sym FSCLK Tcssc TSU THD THI TLO TDO TSCCS TCSH TCS1 TCS0 TSPIR TSPIF
*
Parameter is characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41232D-page 190
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range. FIGURE 16-1:
3.5 Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
3.0
5.5V 5.0V
2.5
IDD (mA)
2.0
4.0V
1.5
3.0V
1.0
2.0V
0.5
0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz FOSC 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
(c) 2007 Microchip Technology Inc.
DS41232D-page 191
PIC12F635/PIC16F636/639
FIGURE 16-2:
4.0 3.5 3.0 2.5 IDD (mA) 4.0V 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz FOSC 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz 3.0V Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C) 5.5V 5.0V
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EC Mode
2.0V
FIGURE 16-3:
4.0 3.5 3.0
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
Typical IDD vs FOSC Over Vdd HS Mode
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
5.5V 5.0V
2.5 IDD (mA) 2.0 1.5 1.0 0.5 0.0 4 MHz 10 MHz FOSC 16 MHz 4.0V 3.5V 3.0V
4.5V
20 MHz
DS41232D-page 192
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 16-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
Maximum IDD vs FOSC Over Vdd HS Mode 5.0 4.5 4.0 3.5 IDD (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4 MHz 10 MHz FOSC 16 MHz 20 MHz 4.0V 3.5V 3.0V Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C) 5.5V 5.0V 4.5V
FIGURE 16-5:
900 800 700 600 IDD (A) 500
TYPICAL IDD vs. VDD OVER FOSC (XT MODE)
XT Mode
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
4 MHz 400 300 1 MHz 200 100 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
DS41232D-page 193
PIC12F635/PIC16F636/639
FIGURE 16-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)
XT Mode 1,400 Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
1,200
1,000
IDD (A)
800 4 MHz 600
400
1 MHz
200
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 16-7:
800 700 600 500 IDD (A) 400 300
TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE) EXTRC Mode
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
4 MHz
1 MHz 200 100 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS41232D-page 194
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 16-8:
1,400 Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
MAXIMUM IDD vs. VDD OVER FOSC (EXTRC MODE)
EXTRC Mode
1,200
1,000 4 MHz
IDD (A)
800
600
400
1 MHz
200
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 16-9:
80 70 60 50 IDD (A) 40 30
IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz)
LFINTOSC Mode, 31KHZ
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
Maximum
Typical 20 10 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
DS41232D-page 195
PIC12F635/PIC16F636/639
FIGURE 16-10:
70 Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
IDD vs. VDD OVER FOSC (LP Mode LP MODE)
60
50 32 kHz Maximum IDD (A) 40
30
20
32 kHz Typical
10
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 16-11:
1,600 1,400 1,200 1,000 IDD (A) 800
TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
5.5V 5.0V
4.0V
3.0V 600 400 200 0 125 kHz 250 kHz 500 kHz 1 MHz FOSC 2 MHz 4 MHz 8 MHz 2.0V
DS41232D-page 196
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 16-12:
2,000 1,800 1,600 1,400 1,200 IDD (A) 1,000 3.0V 800 600 400 200 0 125 kHz 250 kHz 500 kHz 1 MHz FOSC 2 MHz 4 MHz 8 MHz 2.0V 4.0V Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C) 5.5V 5.0V
MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE)
HFINTOSC
FIGURE 16-13:
0.45 0.40 0.35 0.30 IPD (A) 0.25 0.20 0.15 0.10 0.05 0.0 2.0
TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Typical (Sleep Mode all Peripherals Disabled)
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
(c) 2007 Microchip Technology Inc.
DS41232D-page 197
PIC12F635/PIC16F636/639
FIGURE 16-14:
18.0 16.0 14.0 Max. 125C 12.0 IPD (A) 10.0 8.0 6.0 4.0 2.0 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Max. 85C Typical: Statistical Mean @25C Maximum: Mean + 3 Case Temp) + 3 Maximum: Mean (Worst (-40C to 125C)
MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Maximum (Sleep Mode all Peripherals Disabled)
FIGURE 16-15:
180 160 140 120 IPD (A) 100
COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED)
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
Maximum
Typical 80 60 40 20 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS41232D-page 198
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 16-16:
160 Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
BOR IPD vs. VDD OVER TEMPERATURE
140
120
100 IPD (A) Maximum 80 Typical 60
40
20
0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5
FIGURE 16-17:
3.0
TYPICAL WDT IPD vs. VDD OVER TEMPERATURE
Typical
2.5
Typical: Statistical Mean @25C Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
2.0 IPD (A)
1.5
1.0
0.5
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
DS41232D-page 199
PIC12F635/PIC16F636/639
FIGURE 16-18:
25.0
MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
Maximum
20.0 Max. 125C 15.0 Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
IPD (A)
10.0
5.0
Max. 85C
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 16-19:
30 28 26 24 22 Time (ms) 20
WDT PERIOD vs. VDD OVER TEMPERATURE
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C) Max. (125C) Max. (85C)
Typical 18 16 14 Minimum 12 10 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS41232D-page 200
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 16-20:
30 28 26 Maximum 24 22 Time (ms) 20 Typical 18 16 Minimum 14 12 10 -40C 25C Temperature (C) 85C 125C Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
WDT PERIOD vs. TEMPERATURE OVER VDD (5.0V)
Vdd = 5V
FIGURE 16-21:
140
CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE)
High Range
120
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
100 Max. 125C IPD (A) 80 Max. 85C 60 Typical 40
20
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
DS41232D-page 201
PIC12F635/PIC16F636/639
FIGURE 16-22:
180 160 140 120 Max. 125C IPD (A) 100 Max. 85C 80 Typical 60 40 20 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE)
FIGURE 16-23:
VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
(VDD = 3V, -40xC TO 125xC)
0.8 Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
0.7
Max. 125C
0.6
0.5 VOL (V)
Max. 85C
0.4
0.3
Typical 25C
0.2 Min. -40C 0.1
0.0 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
DS41232D-page 202
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 16-24:
0.45 Typical: Statistical Mean @25C Typical: Statistical Case @25xC Maximum: Mean (Worst Mean Temp) + 3 Maximum: Meas + 3 to 125xC) (-40xC (-40C to 125C)
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
0.40
Max. 125C Max. 85C
0.35
0.30
VOL (V)
0.25 Typ. 25C 0.20
0.15
Min. -40C
0.10
0.05
0.00 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
FIGURE 16-25:
3.5
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.0 Max. -40C Typ. 25C
2.5
Min. 125C 2.0 VOH (V) 1.5 Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C) 1.0 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 IOH (mA) -2.5 -3.0 -3.5 -4.0 (c) 2007 Microchip Technology Inc.
DS41232D-page 203
PIC12F635/PIC16F636/639
FIGURE 16-26:
5.5
VOH vs. IOH OVER TEMPERATURE TO 125xC) (VDD = 5V, -40xC (VDD = 5.0V)
5.0 Max. -40C
Typ. 25C 4.5 VOH (V) Min. 125C
4.0
3.5
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 IOH (mA) -3.0 -3.5 -4.0 -4.5 -5.0
FIGURE 16-27:
1.7
TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(TTL Input, -40xC TO 125xC)
1.5
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C) Max. -40C
1.3 VIN (V) Typ. 25C 1.1 Min. 125C 0.9
0.7
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS41232D-page 204
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 16-28: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(ST Input, -40xC TO 125xC) 4.0 VIH Max. 125C 3.5 Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
VIH Min. -40C
3.0
VIN (V)
2.5
2.0 VIL Max. -40C 1.5 VIL Min. 125C
1.0
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 16-29:
45.0 40.0 35.0 30.0 IPD (mA) 25.0 20.0 15.0 10.0 5.0 0.0 2.0
T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz)
Typical: Statistical Mean @25C Maximum: Mean (Worst 125xC) Maximum: Mean + 3 toCase Temp) + 3 (-40xC (-40C to 125C) Max. 125C
Max. 85C
Typ. 25C
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
(c) 2007 Microchip Technology Inc.
DS41232D-page 205
PIC12F635/PIC16F636/639
FIGURE 16-30:
1000 900 800 Response Time (nS) 700 600 500 400 300 200 100 0 2.0 2.5 VDD (V) 4.0 5.5 Typ. 25C Min. -40C Note: VCM = VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM + 100MV to VCM - 20MV Max. 125C
COMPARATOR RESPONSE TIME (RISING EDGE)
531 806
Max. 85C
FIGURE 16-31:
1000 900 800 700 Response Time (nS) 600 500 400 300 200 100 0 Note:
COMPARATOR RESPONSE TIME (FALLING EDGE)
Max. 125C
VCM = VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM - 100MV to VCM + 20MV
Max. 85C
Typ. 25C Min. -40C
2.0
2.5 VDD (V)
4.0
5.5
DS41232D-page 206
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 16-32:
45,000 40,000 35,000 30,000 Frequency (Hz) 25,000 20,000 15,000 10,000 5,000 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Min. 85C Min. 125C Typ. 25C
LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz)
LFINTOSC 31Khz
Max. -40C
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
FIGURE 16-33:
16
TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
14 85C 12 25C 10 Time (s) -40C 8
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
6
4
2
0 2.0
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
(c) 2007 Microchip Technology Inc.
DS41232D-page 207
PIC12F635/PIC16F636/639
FIGURE 16-34:
25
MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
-40C to +85C
20
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C)
Time (s)
15 85C 25C 10 -40C
5
0 2.0
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
FIGURE 16-35:
10 9 8 7
MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
-40C to +85C
Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 (-40C to 125C) 85C
Time (s)
6 25C 5 -40C 4 3 2 1 0 2.0
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
DS41232D-page 208
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 16-36:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25C)
FIGURE 16-37:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0
TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85C)
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
(c) 2007 Microchip Technology Inc.
DS41232D-page 209
PIC12F635/PIC16F636/639
FIGURE 16-38:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125C)
FIGURE 16-39:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40C)
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
DS41232D-page 210
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
17.0
17.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC XXXXXXXX XXXXYYWW NNN 8-Lead DFN (4x4x0.9 mm) Example 12F635/P e3 017 0610
Example 12F635/ SN e3 0610 017 Example
XXXXXX XXXXXX YYWW NNN
8-Lead DFN-S (6x5 mm)
PIC12F 635/MF 0610 017
Example
XXXXXXX XXXXXXX XXYYWW NNN
PICXXF XXX-I/ MF0610 017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
*
Standard PIC device marking consists of Microchip part number, year code, week code and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 2007 Microchip Technology Inc.
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17.1 Package Marking Information (Continued)
14-Lead PDIP XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example PIC16F636-I/P 0610017
14-Lead SOIC XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example PIC16F636 -I/SL e3 0610017
14-Lead TSSOP
Example
XXXXXXXX YYWW NNN
F636/ST 0610 017
16-Lead QFN
Example
XXXXXXX XXXXXXX YYWWNNN
16F636 -I/ML 0610017
20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example PIC16F639 -I/SS e3 0610017
DS41232D-page 212
(c) 2007 Microchip Technology Inc.
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17.2 Package Details
The following sections give the technical details of the packages.
8-Lead Plastic Dual In-Line (P or PA) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N
NOTE 1 E1
1
2 D
3 E A2
A
A1 e b1 b
L
c
eB
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .115 .015 .290 .240 .348 .115 .008 .040 .014 - MIN
INCHES NOM 8 .100 BSC - .130 - .310 .250 .365 .130 .010 .060 .018 - .210 .195 - .325 .280 .400 .150 .015 .070 .022 MAX
.430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-018B
(c) 2007 Microchip Technology Inc.
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8-Lead Plastic Small Outline (SN or OA) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D e N
E E1
NOTE 1 1 2 3 b h c h
A
A2
A1
L L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.17 0.31 5 5 0.25 0.40 - 1.25 0.10 MIN
MILLIMETERS NOM 8 1.27 BSC - - - 6.00 BSC 3.90 BSC 4.90 BSC - - 1.04 REF - - - - - 8 0.25 0.51 15 0.50 1.27 1.75 - 0.25 MAX
15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-057B
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(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
8-Lead Plastic Dual Flat, No Lead Package (MD) - 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N e N L
b
E
K EXPOSED PAD
E2
1 NOTE 1
2 TOP VIEW D2
2
1
NOTE 1
BOTTOM VIEW
A3 A
A1 NOTE 2
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Length Exposed Pad Width Overall Width Exposed Pad Length Contact Width Contact Length N e A A1 A3 D E2 E D2 b L 0.00 0.25 0.30 0.00 0.80 0.00 MIN MILLIMETERS NOM 8 0.80 BSC 0.90 0.02 0.20 REF 4.00 BSC 2.20 4.00 BSC 3.00 0.30 0.55 3.60 0.35 0.65 - 2.80 1.00 0.05 MAX
Contact-to-Exposed Pad K 0.20 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-131C
(c) 2007 Microchip Technology Inc.
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8-Lead Plastic Dual Flat, No Lead Package (MF) - 6x5 mm Body [DFN-S]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
e b L N
D N K E EXPOSED PAD NOTE 1 1 2 TOP VIEW
E2
2 D2
1
NOTE 1
BOTTOM VIEW
A A3
A1
NOTE 2
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Length Overall Width Exposed Pad Length Exposed Pad Width Contact Width Contact Length N e A A1 A3 D E D2 E2 b L 3.90 2.20 0.35 0.50 0.80 0.00 MIN MILLIMETERS NOM 8 1.27 BSC 0.85 0.01 0.20 REF 5.00 BSC 6.00 BSC 4.00 2.30 0.40 0.60 4.10 2.40 0.48 0.75 - 1.00 0.05 MAX
Contact-to-Exposed Pad K 0.20 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-122B
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(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
14-Lead Plastic Dual In-Line (P or PD) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N
NOTE 1
E1
1
2
3 D E A2 L c
A
A1 b
b1 e
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .115 .015 .290 .240 .735 .115 .008 .045 .014 - MIN INCHES NOM 14 .100 BSC - .130 - .310 .250 .750 .130 .010 .060 .018 - .210 .195 - .325 .280 .775 .150 .015 .070 .022 MAX
eB
.430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-005B
(c) 2007 Microchip Technology Inc.
DS41232D-page 217
PIC12F635/PIC16F636/639
14-Lead Plastic Small Outline (SL or OD) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1 NOTE 1 1 2 b 3 e h h A2 c
A
A1
L L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.17 0.31 5 5 0.25 0.40 - 1.25 0.10 MIN
MILLIMETERS NOM 14 1.27 BSC - - - 6.00 BSC 3.90 BSC 8.65 BSC - - 1.04 REF - - - - - 8 0.25 0.51 15 0.50 1.27 1.75 - 0.25 MAX
15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-065B
DS41232D-page 218
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1
NOTE 1 1 b A A2 c 2 e
A1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Footprint Foot Angle Lead Thickness N e A A2 A1 E E1 D L L1 c
L1
MILLIMETERS MIN NOM 14 0.65 BSC - 0.80 0.05 4.30 4.90 0.45 0 0.09 - 1.00 - 6.40 BSC 4.40 5.00 0.60 1.00 REF - - 8 0.20 4.50 5.10 0.75 1.20 1.05 0.15 MAX
L
Lead Width b 0.19 - 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-087B
(c) 2007 Microchip Technology Inc.
DS41232D-page 219
PIC12F635/PIC16F636/639
16-Lead Plastic Quad Flat, No Lead Package (ML) - 4x4x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D EXPOSED PAD
D2
e E E2 2 1 b
2 1
N TOP VIEW NOTE 1
N BOTTOM VIEW L
K
A A1
A3
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Contact-to-Exposed Pad N e A A1 A3 E E2 D D2 b L K 2.50 0.25 0.30 0.20 2.50 0.80 0.00 MIN
MILLIMETERS NOM 16 0.65 BSC 0.90 0.02 0.20 REF 4.00 BSC 2.65 4.00 BSC 2.65 0.30 0.40 - 2.80 0.35 0.50 - 2.80 1.00 0.05 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-127B
DS41232D-page 220
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1
NOTE 1 12 b e
A
A2
c
A1 L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Lead Thickness Foot Angle Lead Width N e A A2 A1 E E1 D L L1 c b 0.09 0 0.22 - 1.65 0.05 7.40 5.00 6.90 0.55 MIN MILLIMETERS NOM 20 0.65 BSC - 1.75 - 7.80 5.30 7.20 0.75 1.25 REF - 4 - 0.25 8 0.38 2.00 1.85 - 8.20 5.60 7.50 0.95 MAX
L
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-072B
(c) 2007 Microchip Technology Inc.
DS41232D-page 221
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NOTES:
DS41232D-page 222
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2007 Microchip Technology Inc.
DS41232D-page 223
PIC12F635/PIC16F636/639
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS41232D FAX: (______) _________ - _________
Device: PIC12F635/PIC16F636/639 Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41232D-page 224
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
APPENDIX A:
Revision A
This is a new data sheet.
DATA SHEET REVISION HISTORY
Revision B
Added PIC16F639 to the data sheet.
Revision C (12/2006)
Added Characterization data; Updated Package Drawings; Added Comparator Voltage Reference section.
Revision D (03/2007)
Replaced Package Drawings (Rev. AM); Replaced Development Support Section. Updated Product ID System.
(c) 2007 Microchip Technology Inc.
DS41232D-page 225
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NOTES:
DS41232D-page 226
(c) 2007 Microchip Technology Inc.
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INDEX
A
Absolute Maximum Ratings .............................................. 163 AC Characteristics Analog Front-End (AFE) for PIC16F639 ................... 187 Industrial and Extended ............................................ 179 Load Conditions ........................................................ 178 AGC Settling ....................................................................... 99 Analog Front-End Configuration Registers Summary Table ................................................ 123 Analog Front-End (AFE) ..................................................... 97 A/D Data Conversion of RSSI Signal........................ 118 AFE Status Register Bit Condition ............................ 127 AGC .............................................................. 98, 99, 106 AGC Preserve........................................................... 106 Battery Back-up and Batteryless Operation.............. 110 Block Diagrams Bidirectional PKE System Application Example 102 Functional ......................................................... 100 LC Input Path .................................................... 101 Output Enable Filter Timing .............................. 103 Output Enable Filter Timing (Detailed) ............. 104 Carrier Clock Detector ................................................ 98 Carrier Clock Output ................................................. 114 Examples .......................................................... 115 Command Decoder/Controller .................................. 121 Configuration Registers ............................................ 122 Data Slicer .................................................................. 98 Demodulator ....................................................... 98, 111 De-Q'ing of Antenna Circuit ...................................... 110 Error Detection.......................................................... 109 Factory Calibration.................................................... 110 Fixed Gain Amplifiers.................................................. 98 Input Sensitivity Control ............................................ 105 LF Field Powering/Battery Back-up Examples .......................................................... 110 LFDATA Output Selection......................................... 111 Case I ............................................................... 112 Case II .............................................................. 112 Low Current Modes Operating .......................................................... 109 Sleep................................................................. 109 Standby............................................................. 109 Modulation Circuit ....................................................... 97 Modulation Depth...................................................... 107 Examples .......................................................... 108 Output Enable Filter .................................................... 98 Configurable Smart ........................................... 103 Output Enable Filter Timing (Table).......................... 105 Power-on Reset ........................................................ 111 RF Limiter ................................................................... 97 RSSI.................................................................... 98, 116 Output Path Diagram ........................................ 116 Power-up Sequence Diagram........................... 118 SPI Read Sequence Diagram........................... 120 SPI Write Sequence Diagram ........................... 119 RSSI Output Current vs. Input Signal Level Example ............................................................ 117 Sensitivity Control ....................................................... 97 Soft Reset ................................................................. 107 SPI Interface Timing Diagram................................... 122 Timers ................................................................... 98, 99 Alarm .................................................................. 99 Auto Channel Selection ...................................... 98 Inactivity ............................................................. 99 Period ................................................................. 99 Preamble Counters............................................. 99 Pulse Width ........................................................ 99 RC Oscillator ...................................................... 98 Tuning Capacitor ........................................................ 97 Variable Attenuator..................................................... 97 Analog Input Connection Considerations ........................... 73 Assembler MPASM Assembler .................................................. 160
B
Block Diagrams Analog Input Model..................................................... 73 Clock Source .............................................................. 35 Comparator................................................................. 71 Comparator C1 ........................................................... 72 Comparator C2 ........................................................... 72 Comparator Modes..................................................... 75 Crystal Operation........................................................ 38 External RC Mode ...................................................... 39 Fail-Safe Clock Monitor (FSCM)................................. 45 Functional (AFE)....................................................... 100 In-Circuit Serial Programming Connection ............... 147 Interrupt Logic........................................................... 140 On-Chip Reset Circuit............................................... 131 PIC12F635 Device ....................................................... 9 PIC16F636 Device ..................................................... 10 PIC16F639 Device ..................................................... 11 RA0 Pin ...................................................................... 52 RA1 Pin ...................................................................... 53 RA2 Pin ...................................................................... 53 RA3 Pin ...................................................................... 54 RA4 Pin ...................................................................... 55 RA5 Pin ...................................................................... 55 RC0 and RC1 Pins ..................................................... 58 RC2, RC3 and RC5 Pins ............................................ 58 RC4 Pin ...................................................................... 59 Recommended MCLR Circuit................................... 133 Resonator Operation .................................................. 38 Timer1 ........................................................................ 65 TMR0/WDT Prescaler ................................................ 61 Watchdog Timer (WDT)............................................ 143 Brown-out Reset (BOR).................................................... 134 Associated ................................................................ 135 Specifications ........................................................... 183 Timing and Characteristics ................................. 87, 182
C
C Compilers MPLAB C18.............................................................. 160 MPLAB C30.............................................................. 160 Clock Sources External Modes........................................................... 37 EC ...................................................................... 37 HS ...................................................................... 38 LP ....................................................................... 38 OST .................................................................... 37 RC ...................................................................... 39 XT ....................................................................... 38 Internal Modes............................................................ 39 Frequency Selection........................................... 41 HFINTOSC ......................................................... 39
(c) 2007 Microchip Technology Inc.
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INTOSC .............................................................. 39 INTOSCIO........................................................... 39 LFINTOSC .......................................................... 41 Clock Switching................................................................... 43 CMCON0 Register .............................................................. 80 CMCON1 Register .............................................................. 82 Code Examples Assigning Prescaler to Timer0 .................................... 62 Assigning Prescaler to WDT ....................................... 62 Data EEPROM Read .................................................. 93 Data EEPROM Write .................................................. 93 Indirect Addressing ..................................................... 32 Initializing PORTA ....................................................... 47 Initializing PORTC....................................................... 57 Saving Status and W Registers in RAM ................... 142 Ultra Low-Power Wake-up Initialization ...................... 51 Write Verify ................................................................. 93 Code Protection ................................................................ 146 Comparator ......................................................................... 71 Associated registers.................................................... 85 C2OUT as T1 Gate ..................................................... 81 Configurations ............................................................. 74 I/O Operating Modes................................................... 74 Interrupts ..................................................................... 77 Operation .............................................................. 71, 76 Operation During Sleep .............................................. 79 Response Time ........................................................... 77 Synchronizing CxOUT w/Timer1................................. 81 Comparator Voltage Reference (CVREF) Response Time ........................................................... 77 Specifications .................................................... 185, 186 Comparator Voltage Reference (CVREF) ............................ 83 Effects of a Reset........................................................ 79 Specifications ............................................................ 185 Comparators C2OUT as T1 Gate ..................................................... 66 Effects of a Reset........................................................ 79 Specifications ............................................................ 185 CONFIG Register.............................................................. 130 Configuration Bits.............................................................. 129 CPU Features ................................................................... 129 Customer Change Notification Service ............................. 223 Customer Notification Service........................................... 223 Customer Support ............................................................. 223 EECON1 Register............................................................... 92 EECON2 (EEPROM Control 2) Register ............................ 92 EEDAT Register ................................................................. 91 EEPROM Data Memory Reading ...................................................................... 93 Write Verify ................................................................. 93 Writing ........................................................................ 93 Electrical Specifications .................................................... 163 Errata .................................................................................... 7
F
Fail-Safe Clock Monitor ...................................................... 45 Fail-Safe Condition Clearing....................................... 45 Fail-Safe Detection ..................................................... 45 Fail-Safe Operation..................................................... 45 Reset or Wake-up from Sleep .................................... 45 Firmware Instructions ....................................................... 149 Fuses. See Configuration Bits
G
General Purpose Register (GPR) File ................................ 18
I
ID Locations...................................................................... 146 In-Circuit Debugger........................................................... 147 In-Circuit Serial Programming (ICSP)............................... 147 Indirect Addressing, INDF and FSR Registers ................... 32 Instruction Format............................................................. 149 Instruction Set................................................................... 149 ADDLW..................................................................... 151 ADDWF..................................................................... 151 ANDLW..................................................................... 151 ANDWF..................................................................... 151 BCF .......................................................................... 151 BSF........................................................................... 151 BTFSC ...................................................................... 151 BTFSS ...................................................................... 152 CALL......................................................................... 152 CLRF ........................................................................ 152 CLRW ....................................................................... 152 CLRWDT .................................................................. 152 COMF ....................................................................... 152 DECF ........................................................................ 152 DECFSZ ................................................................... 153 GOTO ....................................................................... 153 INCF ......................................................................... 153 INCFSZ..................................................................... 153 IORLW ...................................................................... 153 IORWF...................................................................... 153 MOVF ....................................................................... 154 MOVLW .................................................................... 154 MOVWF .................................................................... 154 NOP .......................................................................... 154 RETFIE ..................................................................... 155 RETLW ..................................................................... 155 RETURN................................................................... 155 RLF ........................................................................... 156 RRF .......................................................................... 156 SLEEP ...................................................................... 156 SUBLW ..................................................................... 156 SUBWF..................................................................... 157 SWAPF ..................................................................... 157 XORLW .................................................................... 157 XORWF .................................................................... 157 Summary Table ........................................................ 150 INTCON Register................................................................ 28
D
Data EEPROM Memory Associated Registers .................................................. 94 Code Protection .................................................... 91, 94 Protection Against Spurious Write .............................. 94 Using ........................................................................... 93 Data Memory....................................................................... 17 DC and AC Characteristics Graphs and Tables ................................................... 191 DC Characteristics Extended (PIC12F635/PIC16F636) .......................... 169 Industrial (PIC12F635/PIC16F636)........................... 167 Industrial (PIC16F639) .............................................. 174 Industrial/Extended (PIC12F635/PIC16F636) .. 166, 171 Industrial/Extended (PIC16F639)...................... 173, 175 Development Support ....................................................... 159 Device Overview ................................................................... 9
E
EEADR Register ................................................................. 91 EECON1 (EEPROM Control 1) Register ............................ 92
DS41232D-page 228
(c) 2007 Microchip Technology Inc.
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Internal Oscillator Block INTOSC Specifications............................................ 180, 181 Internet Address................................................................ 223 Interrupts ........................................................................... 139 Associated Registers ................................................ 141 Comparator ................................................................. 77 Context Saving.......................................................... 142 Data EEPROM Memory Write .................................... 92 Interrupt-on-Change.................................................... 50 PORTA Interrupt-on-change ..................................... 140 RA2/INT .................................................................... 139 Timer0....................................................................... 140 TMR1 .......................................................................... 67 INTOSC Specifications ............................................. 180, 181 IOCA Register ..................................................................... 50
P
Packaging ......................................................................... 211 Details....................................................................... 213 Marking..................................................................... 211 PCL and PCLATH............................................................... 32 Stack........................................................................... 32 PCON Register ................................................................... 31 PICSTART Plus Development Programmer..................... 162 PIE1 Register ..................................................................... 29 Pin Diagrams ............................................................ 3, 4, 5, 6 Pinout Descriptions PIC12F635 ................................................................. 12 PIC16F636 ................................................................. 13 PIC16F639 ................................................................. 14 PIR1 Register ..................................................................... 30 PLVD Associated Registers.................................................. 89 PORTA ............................................................................... 47 Additional Pin Functions ............................................. 47 Interrupt-on-Change ........................................... 50 Ultra Low-Power Wake-up............................ 47, 51 Weak Pull-down.................................................. 47 Weak Pull-up ...................................................... 47 Associated Registers.................................................. 56 Pin Descriptions and Diagrams .................................. 52 RA0/C1IN+/ICSPDAT/ULPWU Pin............................. 52 RA1/C1IN-/Vref/ICSPCLK Pin .................................... 53 RA2/T0CKI/INT/C1OUT Pin ....................................... 53 RA3/MCLR/VPP PIN .................................................... 54 RA4/T1G/OSC2/CLKOUT Pin .................................... 55 RA5/T1CKI/OSC1/CLKIN Pin..................................... 55 Specifications ........................................................... 181 PORTA Register ................................................................. 48 PORTC ............................................................................... 57 Associated Registers.................................................. 59 RC0/C2IN+ Pin ........................................................... 58 RC2 Pin ...................................................................... 58 RC3 Pin ...................................................................... 58 RC4/C2OUT Pin ......................................................... 59 RC5 Pin ...................................................................... 58 Specifications ........................................................... 181 PORTC Register................................................................. 57 Power Control (PCON) Register....................................... 135 Power-Down Mode (Sleep)............................................... 145 Power-on Reset ................................................................ 132 Power-up Timer (PWRT) .................................................. 132 Specifications ........................................................... 183 Precision Internal Oscillator Parameters .......................... 181 Prescaler Shared WDT/Timer0................................................... 62 Switching Prescaler Assignment ................................ 62 Product Identification ........................................................ 231 Program Memory ................................................................ 17 Program Memory Map and Stack PIC12F635 ................................................................. 17 PIC16F636/639 .......................................................... 17 Programmable Low-Voltage Detect (PLVD) Module .......... 87 Programming, Device Instructions.................................... 149
K
KEELOQ ............................................................................... 95
L
Load Conditions ................................................................ 178
M
MCLR ................................................................................ 132 Internal ...................................................................... 132 Memory Organization.......................................................... 17 Data ............................................................................ 17 Data EEPROM Memory.............................................. 91 Program ...................................................................... 17 Microchip Internet Web Site .............................................. 223 MPLAB ASM30 Assembler, Linker, Librarian ................... 160 MPLAB ICD 2 In-Circuit Debugger ................................... 161 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 161 MPLAB Integrated Development Environment Software .. 159 MPLAB PM3 Device Programmer .................................... 161 MPLAB REAL ICE In-Circuit Emulator System................. 161 MPLINK Object Linker/MPLIB Object Librarian ................ 160
O
OPCODE Field Descriptions ............................................. 149 OPTION Register ................................................................ 27 OPTION_REG Register ...................................................... 63 OSCCON Register .............................................................. 36 Oscillator Associated registers.............................................. 46, 69 Oscillator Module ................................................................ 35 EC ............................................................................... 35 HFINTOSC.................................................................. 35 HS ............................................................................... 35 INTOSC ...................................................................... 35 INTOSCIO................................................................... 35 LFINTOSC .................................................................. 35 LP................................................................................ 35 RC............................................................................... 35 RCIO ........................................................................... 35 XT ............................................................................... 35 Oscillator Parameters ....................................................... 180 Oscillator Specifications .................................................... 179 Oscillator Start-up Timer (OST) Specifications............................................................ 183 Oscillator Switching Fail-Safe Clock Monitor............................................... 45 Two-Speed Clock Start-up.......................................... 43 OSCTUNE Register ............................................................ 40
R
Reader Response............................................................. 224 Read-Modify-Write Operations ......................................... 149 Registers Analog Front-End (AFE) AFE STATUS Register 7 .................................. 127
(c) 2007 Microchip Technology Inc.
DS41232D-page 229
PIC12F635/PIC16F636/639
Column Parity Register 6 .................................. 126 Configuration Register 0 ................................... 123 Configuration Register 1 ................................... 124 Configuration Register 2 ................................... 124 Configuration Register 3 ................................... 125 Configuration Register 4 ................................... 125 Configuration Register 5 ................................... 126 CMCON0 (Comparator Control 0) .............................. 80 CMCON0 (Comparator Control) Register ................... 79 CMCON1 (Comparator Control 1) .............................. 82 CMCON1 (Comparator Control) Register ................... 82 CONFIG (Configuration Word).................................. 130 EEADR (EEPROM Address) ...................................... 91 EECON1 (EEPROM Control 1)................................... 92 EEDAT (EEPROM Data) ............................................ 91 INTCON (Interrupt Control) ......................................... 28 IOCA (Interrupt-on-change PORTA) ........................... 50 LVDCON (Low-Voltage Detect Control)...................... 89 OPTION_REG (OPTION) ........................................... 27 OPTION_REG (Option) .............................................. 63 OSCCON (Oscillator Control) ..................................... 36 OSCTUNE (Oscillator Tuning) .................................... 40 PCON (Power Control Register) ................................. 31 PIE1 (Peripheral Interrupt Enable 1) ........................... 29 PIR1 (Peripheral Interrupt Request 1) ........................ 30 PORTA........................................................................ 48 PORTC ....................................................................... 57 Reset Values............................................................. 137 Reset Values (Special Registers) ............................. 138 STATUS ...................................................................... 26 T1CON ........................................................................ 68 TRISA (Tri-State PORTA) ........................................... 48 TRISC (Tri-State PORTC) .......................................... 57 VRCON (Voltage Reference Control) ......................... 84 WDA (Weak Pull-up/Pull-down Direction PORTA)...... 49 WDTCON (Watchdog Timer Control)........................ 144 WPUDA (Weak Pull-up/Pull-down Enable PORTA).... 49 Reset................................................................................. 131 Revision History ................................................................ 225 T0CKI ......................................................................... 62 Timer1................................................................................. 64 Associated registers ................................................... 69 Asynchronous Counter Mode ..................................... 66 Reading and Writing ........................................... 66 Interrupt ...................................................................... 67 Modes of Operation .................................................... 64 Operation During Sleep .............................................. 67 Oscillator..................................................................... 66 Prescaler .................................................................... 66 Specifications ........................................................... 184 Timer1 Gate Inverting Gate ..................................................... 66 Selecting Source .......................................... 66, 81 Synchronizing CxOUT w/Timer1 ........................ 81 TMR1H Register ......................................................... 64 TMR1L Register.......................................................... 64 Timers Timer1 T1CON ............................................................... 68 Timing Diagrams Brown-out Reset (BOR)...................................... 87, 182 Brown-out Reset Situations ...................................... 134 CLKOUT and I/O ...................................................... 181 Clock Timing ............................................................. 179 Comparator Output ..................................................... 71 Fail-Safe Clock Monitor (FSCM)................................. 46 INT Pin Interrupt ....................................................... 141 Internal Oscillator Switch Timing ................................ 42 Reset, WDT, OST and Power-up Timer ................... 182 Time-out Sequence on Power-up (Delayed MCLR) . 136 Time-out Sequence on Power-up (MCLR with VDD) 136 Timer0 and Timer1 External Clock ........................... 184 Timer1 Incrementing Edge ......................................... 67 Two Speed Start-up.................................................... 44 Wake-up from Sleep through Interrupt ..................... 146 Timing Parameter Symbology .......................................... 178 TRISA ................................................................................. 47 TRISA Register................................................................... 48 TRISC Register................................................................... 57 Two-Speed Clock Start-up Mode........................................ 43
S
Software Simulator (MPLAB SIM)..................................... 160 Special Function Registers (SFR)....................................... 18 Maps PIC12F635.......................................................... 19 PIC16F636/639................................................... 20 Summary PIC12F635, Bank 0............................................. 21 PIC12F635, Bank 1............................................. 22 PIC12F635/PIC16F636/639, Bank 2 .................. 25 PIC16F636/639, Bank 0...................................... 23 PIC16F636/639, Bank 1...................................... 24 SPI Timing Analog Front-End (AFE) for PIC16F639 ................... 190 STATUS Register................................................................ 26
U
Ultra Low-Power Wake-up................................ 13, 14, 47, 51
V
Voltage Reference. See Comparator Voltage Reference (CVREF) Voltage References Associated registers ................................................... 85
W
Wake-up from Sleep ......................................................... 145 Wake-up Reset (WUR) ..................................................... 132 Wake-up using Interrupts.................................................. 145 Watchdog Timer (WDT).................................................... 143 Associated Registers ................................................ 144 Control ...................................................................... 143 Oscillator................................................................... 143 Specifications ........................................................... 183 WDA Register ..................................................................... 49 WDTCON Register ........................................................... 144 WPUDA Register ................................................................ 49 WWW Address ................................................................. 223 WWW, On-Line Support ....................................................... 7
T
T1CON Register.................................................................. 68 Thermal Considerations .................................................... 177 Time-out Sequence........................................................... 135 Timer0 ................................................................................. 61 Associated Registers .................................................. 63 External Clock ............................................................. 62 Interrupt....................................................................... 63 Operation .............................................................. 61, 64 Specifications ............................................................ 184
DS41232D-page 230
(c) 2007 Microchip Technology Inc.
PIC12F635/PIC16F636/639
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device: PIC12F635(1, 2), PIC16F636(1, 2), PIC16F639(1, 2) VDD range 2.0V to 5.5V PIC12F635-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 PIC12F635-I/S = Industrial Temp., SOIC package, 20 MHz
Temperature Range:
I E
= -40C to +85C = -40C to +125C
(Industrial) (Extended)
Package:
MD MF ML P SL SN SS ST
= = = = = = = =
Dual-Flat, No Leads, 8-pin (4x4x0.9 mm) Dual-Flat, No Leads, Saw Sing. (6x5 mm) Dual-Flat, No Leads, 16-pin (4x4x0.9 mm) Plastic DIP (300 mil body, 5.30 mm) 14-lead Small Outline (3.90 mm) 8-lead Small Outline (3.90 mm) 20-Lead Plastic Shrink Small Outline (5.30 mm) 14-Lead Thin Shrink Small Outline (4.4 mm)
Note 1: 2:
F T
= Standard Voltage Range = in tape and reel PLCC.
Pattern:
3-Digit Pattern Code for QTP (blank otherwise)
(c) 2007 Microchip Technology Inc.
DS41232D-page 231
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
12/08/06
DS41232D-page 232
(c) 2007 Microchip Technology Inc.

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